mobile | classic  
Dataweek Electronics & Communications Technology Magazine





Follow us on:
Follow us on Facebook Share via Twitter Share via LinkedIn


Search...

Electronics Buyers' Guide

Electronics Manufacturing & Production Handbook 2017


 

DFT tool for Mentor Graphics PADS
19 April 2017, Design Automation

Developed by XJTAG, the free DFT Assistant software for Mentor Graphics’ PADS platform increases the design for test (DFT) and debug capabilities of the schematic capture and PCB design environment.

Printed circuit boards (PCBs) are increasingly densely populated and access to pins under many packages, such as ball grid arrays (BGA), is virtually impossible. JTAG was designed to solve the problem of access and so it is now vitally important to get the JTAG chain right at the design stage. Failure to identify and fix design errors at an early stage can result in a board re-spin and a costly delay to a project. XJTAG DFT Assistant helps validate correct JTAG chain connectivity, through full integration with the PADS schematic capture environment.

“PADS products now include the XJTAG DFT Assistant that provides engineers with a free, easy-to-use interface to check if JTAG chains are correctly connected and terminated at the schematic capture stage, long before the PCB is produced,” said Jim Martens, product marketing manager, PADS Solutions Group. “By detecting and correcting these faults earlier, companies do save both time and money. This software is free for PADS users of VX.2.1 or higher and can be downloaded from www.xjtag.com/pads.”

The XJTAG DFT Assistant comprises of two key elements: the XJTAG Chain Checker, and the XJTAG Access Viewer.

XJTAG Chain Checker identifies common errors in a JTAG scan chain, such as incorrectly connected test access ports (TAPs). A single connection error would inhibit an entire scan chain from working. The checker identifies connection errors and reports them to the developer during the design process. Incorrectly terminated TAPs are also identified.

XJTAG Access Viewer overlays the extent of boundary scan access onto the schematic diagram, allowing users to instantly see which components are accessible using boundary scan, and where test coverage could be further extended. Engineers can highlight the nets individually to show read, write, power/ground and the nets that don’t have any JTAG access on the schematic.

While the first prototype is being manufactured, XJTAG DFT Assistant allows engineers to export a preliminary XJTAG project from the PADS schematic capture environment to the XJTAG development software, where additional tests can be developed. These can then be used to test real hardware, as soon as it’s available.

For more information contact ASIC Design Services, +27 (0)11 315 8316, info@asic.co.za, www.asic.co.za


Credit(s)
Supplied By: ASIC Design Services
Tel: +27 11 315 8316
Fax: +27 11 315 1711
Email: info@asic.co.za
www: www.asic.co.za
  Follow us on Facebook Share via Twitter Share via LinkedIn    

Further reading:

  • Designing for testability
    19 April 2017, EDA Technologies, Design Automation
    The overall cost to produce a completed printed circuit board (PCB) can be broken down into several basic categories: the cost of manufacturing the blank PCB, the cost of components, the assembly costs, ...
  • DesignSpark nets half a million users
    19 April 2017, RS Components (SA), Design Automation, News
    DesignSpark, an online electronics engineering community launched in 2010 by RS Components, recently welcomed its 500 000th member. The DesignSpark ecosystem offers online design resources and free ...
  • Motor control plug-in for MPLAB X
    19 April 2017, Avnet South Africa, Design Automation
    Microchip has rolled out an advanced motor control software plug-in for its MPLAB X integrated development environment (IDE) with auto-tuning and self-commissioning capability. The plug-in, called motorBench ...
  • Proteus 8.6 released, now simulating turtles
    22 March 2017, Dizzy Enterprises, Design Automation
    Version 8.6 of Proteus simulation and PCB design software adds new features such as STM32F103xx microcontroller simulation and serpentine track length matching, but perhaps one of the more novel new features ...
  • Microsemi unveils PolarFire FPGA
    22 March 2017, ASIC Design Services, Programmable Logic
    Microsemi unveiled the new cost-optimised PolarFire field programmable gate array (FPGA) product family, delivering what the firm claims is the industry’s lowest power at mid-range densities with 12,7 ...
  • Altium upgrades Vault to version 3.0
    22 March 2017, EDA Technologies, Design Automation
    Altium has launched an all-new version of its PCB component and design data management solution with Altium Vault 3.0, as a complement to its PCB design software Altium Designer 17. The firm says it ...
  • Graphical configurator for STM8 designs
    22 March 2017, Design Automation, DSP, Micros & Memory
    STMicroelectronics has made starting new designs with its popular 8-bit STM8 microcontrollers easier and faster by introducing the STM8CubeMX graphical configurator. STM8CubeMX supports the complete ...
  • Latest update release for Altium Designer
    31 January 2017, EDA Technologies, Design Automation
    Altium has launched Altium Designer 17, the latest version of its leading PCB design software. The highlights of this newest update are focused on giving designers several advanced new technologies ...
  • Development boards for 32-bit PICs
    31 January 2017, Avnet South Africa, Design Automation
    Newly released by Microchip are two low-cost, rapid prototyping boards for 32-bit applications. The PIC32MX and PIC32MZ Curiosity boards include an integrated programmer debugger and are fully incorporated ...
  • Cadence bestows OrCAD Capture with XJTAG DFT Assistant
    31 January 2017, Cadshop, Design Automation
    Cadence Design Systems has enhanced its OrCAD Capture software to include XJTAG DFT Assistant, an easy-to-use interface that significantly increases the design for test (DFT) and debug capabilities of ...
  • ISP Flash configuration for ARM-based FPGAs
    9 November 2016, ASIC Design Services, Programmable Logic
    XJTAG has extended the capability of its high-speed in-system programming (ISP) technology, XJFlash. The solution effectively brings the benefits of XJFlash to memory devices connected to the processor ...
  • Microchip’s IDE launches into the cloud
    9 November 2016, Avnet South Africa, Design Automation
    Microchip Technology launched MPLAB Xpress, a cloud-based Integrated Development Environment (IDE), the company proclaimed as the easiest way to get started with PIC microcontrollers (MCUs), with zero ...

 
 
         
Contact:
Technews Publishing (Pty) Ltd
1st Floor, Stabilitas House
265 Kent Ave, Randburg, 2194
South Africa
Publications by Technews
Dataweek Electronics & Communications Technology
Electronic Buyers Guide (EBG)

Hi-Tech Security Solutions
Hi-Tech Security Business Directory

Motion Control in Southern Africa
Motion Control Buyers’ Guide (MCBG)

South African Instrumentation & Control
South African Instrumentation & Control Buyers’ Guide (IBG)
Other
Terms & conditions of use, including privacy policy
PAIA Manual





 

         
    Classic | Mobile

Copyright © Technews Publishing (Pty) Ltd. All rights reserved.