UltraScale FPGAs by Xilinx
19 November 2014
News
Programmable Logic
Xilinx’s 20 nm All Programmable UltraScale portfolio delivers an ASIC-class programmable architecture coupled with the Vivado ASIC-strength design suite.
It extends the Kintex and Virtex FPGA and 3D IC families, based on TSMC’s 20SoC process.
These devices deliver next-generation routing, ASIC-like clocking, and enhancements to logic and fabric to eliminate interconnect bottlenecks while supporting consistent device utilisation of more than 90% without performance degradation.
The Kintex UltraScale FPGAs deliver up to 1,16M logic cells, 5520 optimised DSP slices, 76 Mbits of BRAM, 16,3 Gbps backplane-capable transceivers, PCIe Gen3 hard blocks, integrated 100 Gbps Ethernet MAC and 150 Gbps Interlaken IP Cores, and DDR4 memory interfaces.
As for the Virtex UltraScale devices, the largest family member delivers 4,4 M logic cells, 1456 user I/Os, 48 x 16,3 Gbps backplane-capable transceivers and 89 Mbits of Block RAM, delivering 50M equivalent ASIC gates. They include 28 Gbps backplane-capable and 33 Gbps chip-to-optics transceivers, in addition to integrated PCIe Gen3, 100 Gbps Ethernet MAC and 150 Gbps Interlaken IP cores, and DDR4 memory interfaces to support multi-hundred gigabit-per-second levels of system performance with smart processing at full line rates.
UltraScale devices provide the same performance of the logic fabric and key architectural blocks across the portfolio, enabling a scalable and optimised architecture. Moreover, with footprint compatibility between families, the Kintex models provide a clear migration path to Virtex devices.
For more information contact Erich Nast, Avnet Kopp, +27 (0)11 319 8600, erich.nast@avnet.eu, www.avnet.co.za
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