Microchip revealed its new 16 bit dsPIC digital signal controllers which have a 16 bit (data) nonpipelined modified Harvard RISC core that combines the advantages of a high performance 16 bit microcontroller with the high computation speed of a digital signal processor. This provides a tightly coupled, single-chip, single-instruction stream solution for embedded systems designs, according to the company.
Microchip's DSP engine significantly enhances the core's arithmetic capability and throughput and features:
* A high speed 16 bit by 16 bit multiplier.
* A 40 bit adder, two 40 bit saturating accumulators.
* A 40 bit bidirectional barrel shifter.
With performance of 30 MIPS, the 16 bit microcontroller features 94 instructions and 11 addressing modes. The architecture supports up to 4 MB x 24 addressable flash program memory space and up to 32K x 16 data space. The dsPIC instruction set architecture was designed to be highly efficient for C compilers and RTOS and features many high performance peripherals including a fault-tolerant oscillator and up to eight capture and eight compare functions.
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