Programmable Logic


Latest Articles

Full-featured EPROM and flash memory emulators
22 May 2002, Sivan Electronic Supplies
Ceibo's multiROM Series ROM emulators are advanced debugging tools for embedded systems. The multiROM Series ROM emulators are full-featured EPROM and flash memory emulators - ie EPROM or flash memory ...

Read more...
FPGAs specifically designed for radiation-intensive applications
22 May 2002, ASIC Design Services
Actel has announced qualification and availability of its single-chip, 'live-at-power-up' 72 000-gate RT54SX72S antifuse field-programmable gate array (FPGA). Actel also announced that the Defense Supply ...

Read more...
Cadence supports ProASICPlus FPGAs
8 May 2002, ASIC Design Services
Actel has announced that the Cadence NC family of simulators and BuildGates synthesis tool now fully supports Actel's ProASICPLUS family of flash-based FPGAs. For simulation of ProASICPLUS designs, the ...

Read more...
Magitron LED screens leverage high-performance, low-power FPGAs
24 April 2002, ASIC Design Services
NetVision, a supplier of products and services for giant light-emitting diode (LED) screens, has chosen Actel's A54SX72A antifuse field-programmable gate array (FPGA) device for its new Magitron range ...

Read more...
Portable programmer for in-system programmability
10 April 2002, ASIC Design Services
Actel and First Silicon Solutions (FS2) are offering the Flash Pro programmer, which provides in-system programmability (ISP) for Actel's flash-based ProASIC FPGA families, including its new ProASICPLUS ...

Read more...
Million gate flash FPGA breaks density barrier
27 March 2002, ASIC Design Services
Based on a 0,22 µm process, Actel's new single-chip, in-system programmable ProASICPLUS FPGA family will consist of six devices ranging in density from 150 000 to 1-million system gates. The devices are ...

Read more...
Design security in nonvolatile and antifuse FPGAs
13 March 2002, ASIC Design Services
Higher mask cost and increasing minimum lot sizes, two economic trends of the semiconductor industry, are making FPGAs increasingly more cost-effective compared to the competing ASIC solutions. As a result, ...

Read more...
Using external SRAM memory with Actel SX/SX-A FPGAs
13 February 2002, ASIC Design Services
Today's system designs are growing in complexity, requiring larger amounts of memory for high-performance buffers and other local data storage. System designs that require both logic gates and memory ...

Read more...
FPGA vendors go for the hard cell
21 November 2001, ASIC Design Services
Looking to the wider horizon, the signs are that gate arrays will continue to diminish as a viable option for many designs, with many of those that would have taken this approach in the past now migrating to standard cells, at the higher density end of things, while FPGAs continue to eat away at the lower density gate array business

Read more...
ASICs from FPGA prototypes in five weeks
21 November 2001, MB Silicon Systems
Clear Logic has announced availability of production quantities of the first member of its Liberator ASIC family. According to the company, the 50 000 gate Liberator CL10K50V is the world's first device ...

Read more...
Xilinx launches website for FPGA processor solutions
21 November 2001
Xilinx has launched the Processor Central website ( www.xilinx.com/processor), a resource dedicated to the development and integration of processor-based designs using the company's Platform FPGAs. The ...

Read more...
Embeddable, reprogrammable IP cores available on Chartered 0,18 µm process
24 October 2001, ASIC Design Services
Actel has announced the availability of its SRAM-based VariCore embedded programmable gate array (EPGA) intellectual property (IP) cores on the 0,18 µm process from Chartered Semiconductor Manufacturing. ...

Read more...
Bridgeable POS-PHY solutions from 155 Mbps to 10 Gbps
10 October 2001
Altera has announced the availability of the POS-PHY Level 4 MegaCore logic function with Altera's Atlantic on-chip interface. Optimised for Altera's APEX II devices, the POS-PHY Level 4 interface is ...

Read more...
Industry's largest single-chip flash-based FPGAs qualified to industrial specs
10 October 2001, ASIC Design Services
Actel has announced it is shipping the industry's largest flash-based, 'live-at-power-up', field-programmable gate array (FPGA) devices qualified to industrial specifications. The ProASIC A500K180 and ...

Read more...
Partnership to provide conversion path from ProAsic FPGAs to standard cell ASICs
10 October 2001, ASIC Design Services
Actel and Faraday Technology, a leading turnkey ASIC service provider, have said they will provide a low-risk, cost-effective conversion path from current and future generations of Actel's single-chip, ...

Read more...
Next-generation integrated design environment for FPGAs
12 September 2001, ASIC Design Services
Actel has introduced Libero, its next-generation integrated design environment for FPGA development and design. A comprehensive design management environment, Libero integrates industry-leading design ...

Read more...
Interface provides 'network glue' in reference platform
29 August 2001
Altera has announced that Clearwater Networks has successfully implemented its Atlantic interface, integrating various networking functions within its quad-gigabit ethernet hardware reference platform. ...

Read more...
Space-qualified FPGAs with unique hardened latches
15 August 2001, ASIC Design Services
Actel has announced qualification and shipment of the RT54SX32S field-programmable gate array (FPGA), the first member of the company's radiation-tolerant RTSX-S family specifically architected to address ...

Read more...
Socket-compatible replacements for Altera MAX 7256A
15 August 2001, MB Silicon Systems
Clear Logic has introduced a new member of its CL7000A family of 3,3-V Link Processed Logic Devices (LPLDs). The CL7256A is 100% socket-compatible with Altera's MAX 7256A PLD, but has a 45% smaller die, ...

Read more...
FPGA design technique - maintaining phase relationships
1 August 2001, ASIC Design Services
Chip designers often find themselves in a situation where the board layout has been completed before the chip is designed. The FPGA they are targeting must satisfy an external input phase relationship ...

Read more...



<< First   < Previous   Page 12 of 14   Next >   Last >>