|
Logic Lab
Box 7395, Bonaero Park, 1622
|
News from Logic Lab: |
Requirements lifecycle management for FPGA/ASIC designs
12 June 2013, Design Automation, Logic Lab
Aldec announced the launch of Spec-TRACER, a new FPGA/ASIC requirements lifecycle management solution for use in safety-critical industries in which rigorous certification standards exist, such as DO-254 ... |
ASIC/FPGA code analysis tool
6 February 2013, Design Automation, Logic Lab
Aldec’s ALINT design analysis and linting tool identifies critical design issues early in the design stage of ASIC and FPGA designs. The tool points out coding style, functional and structural problems ... |
FPGA design and simulation tool
31 October 2012, Design Automation, Logic Lab
Aldec’s Active-HDL is a Windows-based, integrated FPGA design creation and simulation solution for team-based environments. The tool’s integrated design environment (IDE) includes a full HDL and graphical ... |
Electronics & communications technology news: |
Demystifying quantum
30 April 2024, Editor's Choice
Quantum, often called quantum mechanics, deals with the granular and fuzzy nature of the universe, and the physical behaviour of its smallest particles.
|
The impact of ML in robotics
30 April 2024, Manufacturing / Production Technology, Hardware & Services
The integration of machine learning into robotics has the potential to revolutionise many industries, and particularly the manufacturing sector.
|
Mouser sponsors NCP Cup 2024
30 April 2024, News
The NXP Cup is an EMEA-based autonomous car competition, presented by NXP Semiconductors, which is designed to provide students with real-world experiences in autonomous vehicle programming and building.
|
Qi2 dsPIC33-based reference design
30 April 2024, DSP, Micros & Memory
Powered by a single dsPIC33 Digital Signal Controller, the Qi2 reference design offers efficient control for optimised performance. |
Analysis of switch-mode power supply: inductor violations
30 April 2024, Power Electronics / Power Management, Editor's Choice, Altron Arrow
Common switch-mode power supply (SMPS) design errors are discussed, and their appropriate rectification is specified, with details on complications that arise with the power stage design of DC-DC switching regulators.
|
AC-DC brick PSU
30 April 2024, Power Electronics / Power Management, Conical Technologies
These PSUs have a typical efficiency of up to 92%, and a power factor value of up to 0,99. They are available in 12, 24, 28, 48 and 54 V output versions. |
visit www.dataweek.co.za |
|
|
|
|
|