105 MSps ADC with unique serial interface
12 November 2008
Analogue, Mixed Signal, LSI
Linear Technology introduced a 16-bit, 105 MSps ADC that employs an innovative approach to digital communication between high speed ADCs and FPGAs. The LTC2274’s high-speed 2-wire serial interface greatly reduces the number of data input/output (I/O) lines required between a 16-bit ADC and the FPGA from 16 CMOS or 32 LVDS parallel data lines to a single, self-clocking, differential pair communicating at 2,1 Gbps, freeing up valuable FPGA pins.
Serial data communications offers simplified layout, and requires less board area for routing, while providing the flexibility to route across analog and digital boundaries. In noise-sensitive applications, the serial interface provides an effective isolation barrier between digital and analog circuitry and serves to eliminate coupling between digital outputs to reduce digital feedback.
The LTC2274 output data is serialised according to the JEDEC serial interface specification for data converters (JESD204) using 8b10b encoding, and is compatible with many FPGA high speed interfaces including Xilinx’s Rocket IO, Altera’s Stratix II GX I/O and Lattice’s ECP2M I/O. Applications such as leading edge communications equipment, multichannel systems, space-constrained designs and instrumentation can all benefit from the LTC2274’s unique interface and feature set.
The device offers several unique features to improve overall system design. For high-sensitivity receiver applications, it provides an internal transparent dither circuit that improves the ADC’s SFDR response well beyond 100 dBc for low-level input signals. To avoid any interference from the serial digital outputs, an optional data scrambler is available to randomise the spectrum of the serial link. Serial test patterns are also incorporated to facilitate testing of the serial interface.
While the LTC2274 may be operated at a maximum sampling rate of 105 MSps, the internal PLL may be configured to lock at one of three different sample rate ranges. An on-chip clock duty cycle stabiliser circuit has been implemented to facilitate non-50% clock duty cycles. Separate shutdown pins for the analog and digital sections are provided to conserve power.
The LTC2274 offers signal to noise ratio (SNR) performance of 77,5 dB and spurious free dynamic range (SFDR) of 100 dB at baseband. Ultra-low jitter of 80 fs RMS enables under-sampling of input frequencies up to 500 MHz with excellent noise performance.
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