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Electronics Buyers' Guide

Electronics Manufacturing & Production Handbook 2017


 

Control system advances through high-performance data conversion
31 August 2011, Analogue, Mixed Signal, LSI

Many industrial control systems maintain precise regulation of a critical parameter – electrical, mechanical, thermal or hydraulic – through the use of sophisticated, high-order control loops.

In this era of rapid technological advances, control system designers are facing unprecedented challenges in realising their design goals. Systems must be faster, more accurate and more flexible than ever before, while integrating more functionality into increasingly small enclosures and dissipating less power.

As a result, new solutions are needed that not only push the performance envelope of existing designs and to enable new capabilities. At the core of many industrial control systems is an analog-to-digital converter (ADC). The ADC plays a pivotal role in such systems as power grid monitors, optical networking switches and manufacturing robot systems, translating key signals from the analog domain to digital for digital signal processing. This analog-to-digital conversion must increasingly be performed with high resolution, high speed and low power.

Many control system designers rely on successive approximation register (SAR) ADCs to accurately digitise their critical analog signals. Fundamentally, SAR ADCs are characterised by their ability to acquire a precise snapshot in time of the input signal and to perform the analog-to-digital conversion within a single clock cycle.

SAR ADCs excel at asynchronous ‘start-and-go’ operation since the input is sampled at a precise moment in time and the result is available immediately within the same clock cycle. The ability to quickly and accurately produce conversion results with no cycle latency even after long idle periods (so-called ‘one shot’ operation) makes SAR ADCs ideally suited for control system applications. Other types of ADCs, such as delta-sigma and pipelined ADCs, require multiple clock cycles to complete a single conversion, making them more difficult to use in a control system.

Since many applications require multiple control loops to operate simultaneously in a given system, the footprint and power dissipation of the ADC are also important considerations. For example, channel density is a key selling point for modern optical networking switches. These systems often integrate many small, low-power SAR ADCs to monitor and control the output power level of individual optical channels. Thus, high-resolution, high-speed and low-power SAR ADCs with one-shot accuracy are needed to enable faster, more responsive control systems.

Linear Technology recently introduced a new family of high performance SAR ADCs to meet these challenges. The LTC2379-18 and LTC2380-16 are the first products in a family of pin- and software-compatible SAR ADCs featuring 101 dB SNR at 18 bits and 96 dB SNR at 16 bits from 250 KSps to 2 MSps. This performance is achieved while maintaining low power operation, from 3,75 mW at 250 KSps to 19 mW at 2 MSps. Each device is available in small MSOP-16 or DFN-16 packages. Table 1 summarises the new ADC family.

Table 1. Linear Technology’s SAR ADC family
Table 1. Linear Technology’s SAR ADC family

For the benefit of system designers responsible for evaluating and selecting the ADC, this article discusses several key SAR ADC performance specifications relevant to their use in control systems, in order to reduce the uncertainty involved in selecting the best ADC for control systems and other demanding applications.

Control system requirements

Naturally, high-resolution control systems require high-resolution ADCs to digitise the input signal to finer levels. The ADC must perform the conversion while adding as little noise as possible to the signal chain. It is well known that ADC noise can be reduced by averaging the results of multiple conversions at the expense of lowering the effective conversion rate. A low-noise ADC not only affords accuracy and resolution but also enables higher-speed operation, thus improving the response time of the control system. The designer must trade off the resolution, speed, noise and power requirements to achieve the overall goals of the system.

Noise

System designers may evaluate the noise performance of an SAR ADC through two distinct specifications. For systems that digitise signals with dynamic AC content, the signal-to-noise-ratio (SNR) is a revealing specification. The higher the SNR, the greater the dynamic range between the fundamental signal and the noise floor of the ADC. A low-noise ADC provides more noise margin to the signal processing chain, helping to relax the system design constraints.

Figure 1 shows an FFT plot of the LTC2379-18, an 18-bit 1,6 MSps SAR ADC with 101 dB SNR. The very low noise floor of this high-speed SAR ADC affords flexibility and ease of use in industrial control system design.

Figure 1. FFT plot of LTC2379-18 operating at 18 bits and 1,6 MSps
Figure 1. FFT plot of LTC2379-18 operating at 18 bits and 1,6 MSps

For systems that primarily regulate static DC signals, transition noise is a revealing specification. Transition noise is a direct measure of the code spread at the ADC output when the ADC input is held at a fixed level. The lower the transition noise, the more stable the ADC output, allowing accurate measurements to be made with less averaging. Figure 2 shows the transition noise characteristics of the LTC2380-16, a 16-bit 2 MSps SAR ADC. At less than 0,2 LSB of transition noise, no averaging would be needed to reduce uncertainty in the ADC output, enabling true one-shot operation at high speeds.

Figure 2. Transition noise plot of LTC2380-16 operating at 16 Bits and 2 MSps
Figure 2. Transition noise plot of LTC2380-16 operating at 16 Bits and 2 MSps

Speed

Due to the many competing factors that influence transistor-level design, the ADC noise, speed and power consumption generally trade off with each other. Slower-speed ADCs are often able to maintain lower noise operation than higher-speed ADCs.

When comparing the relative speeds of various SAR ADCs, it is useful to look not only at the claimed sample rate but also at the guaranteed conversion time. This is especially true of serial devices that use a serial peripheral interface (SPI) bus to transfer the conversion result to a digital processor. The claimed throughput of a serial ADC can be increased at the cost of burdening the user with a higher-speed digital interface.

Figure 3 illustrates the typical timing diagram for a no-latency SAR ADC with a serial interface. The total cycle time consists of a conversion time plus an acquisition time. Typically, serial data transfer occurs during the acquisition time window. For a given cycle time, a shorter conversion time allows for a longer serial data transfer window, reducing the required digital interface speed. Of course, a shorter conversion time also minimises the delay from the sampling moment to the digital result, a key consideration for control systems. Thus, it is recommended to pay close attention to the conversion time specification when comparing the relative speeds of various serial ADCs.

Figure 3. Typical timing diagram of 18-Bit serial SAR ADC
Figure 3. Typical timing diagram of 18-Bit serial SAR ADC

Reliability

In addition to the performance specifications, many industrial control system designers must maintain high reliability standards for their products and consequently demand high reliability from key components they select, including the ADC. For quality-conscious applications, it is critical to select ADCs with guaranteed minimum or maximum limits for all key performance specifications such as INL, DNL, SNR and THD.

These specifications should be guaranteed over the full operating temperature range of the application. Users should be especially cautious if these key parameters are guaranteed only at room temperature or only across a small temperature range. The internal building blocks of a high-resolution SAR ADC can exhibit dramatic changes over temperature if they are not designed robustly. Selecting an ADC without guaranteed limits over a wide temperature range introduces unnecessary risk into the design.

Energy efficient solutions

Reducing power dissipation is an important goal of many modern designs, including control systems. In addition to the obvious merits of lower power consumption, many systems are limited by thermal considerations and the ability to remove excess heat from within narrow enclosures. This is especially true of systems that require tens or hundreds of channels to be integrated into a dense circuit board area. Thus, power dissipation and integration density are two key performance metrics in selecting an SAR ADC.

Traditional high-resolution SAR ADC signal chains often require ADC driver amplifiers powered by split supplies. For a 0-5 V signal swing, ±6 V rails are not uncommon. The negative supply is required to maintain good distortion performance in the driver amplifier, even in so-called rail-to-rail output amplifiers, since the output transistors need to maintain a minimum voltage across them to maintain high levels of linearity. This additional negative supply rail dissipates power and is cumbersome to generate and route throughout the PCB.

Given these limitations, power-conscious designs typically eliminate the need for the driver amplifier’s negative supply by attenuating the input signal and utilising only a fraction of the full-scale input signal range. Such an approach relaxes the output swing requirement on the ADC driver amplifier. However, by utilising only a fraction of the available codes and input signal range, the effective resolution of the control system is reduced.

Digital gain compression

To overcome these fundamental limitations, the LTC2379-18 and LTC2380-16 feature a unique digital gain compression (DGC) function, which eliminates the driver amplifier’s negative supply while preserving the full resolution of the ADC. When enabled, the ADC performs a digital scaling function that maps zero-scale code from 0 V to 0,1*VREF and full-scale code from VREF to 0,9*VREF. For a typical reference voltage of 5 V, the full-scale input range is now 0,5 V to 4,5 V, which provides adequate headroom for powering the driving amplifier from a single 6 V supply.

As shown in Figure 4, the DGC feature allows the ADC to generate every code (eg, 218 = 262 144 codes in the case of an 18-bit ADC), including zero-scale and full-scale, while relaxing the output swing requirement on the ADC driver amplifier.

Figure 4. Digital gain compression (DGC) feature enables zero- and full-scale codes from single-supply driver amplifiers
Figure 4. Digital gain compression (DGC) feature enables zero- and full-scale codes from single-supply driver amplifiers

Figure 5 demonstrates a complete signal chain that digitises an industrial ±10 V true bipolar signal to an 18-bit code at 1,6 MSps using a single 6V supply by taking advantage of the DGC feature of the LTC2379-18. This circuit is implemented in the demo system of the LTC2379-18 and achieves 99 dB SNR and over 100 dB THD. The elimination of the driver amplifier’s negative supply while utilising the ADC’s full range and resolution provides a unique solution for modern industrial control systems.

Figure 5. Complete single 6 V supply signal chain digitising an industrial ±10 V true bipolar signal using the LTC2379-18’s digital gain compression (DGC) feature
Figure 5. Complete single 6 V supply signal chain digitising an industrial ±10 V true bipolar signal using the LTC2379-18’s digital gain compression (DGC) feature

For more information contact Kevin Godfrey, Arrow Altech Distribution, +27 (0)11 923 9600, kgodfrey@arrow.altech.co.za, www.arrow.altech.co.za


Credit(s)
Supplied By: Altron Arrow
Tel: +27 11 923 9600
Fax: +27 11 923 9884
Email: info@arrow.altech.co.za
www: www.altronarrow.com
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