Pentek announced its most recent addition to the Jade architecture family, the Jade Model 71871, a four-channel 1,25 GHz D/A converter XMC for RF and IF waveform generation. The Model 71871 combines two Texas Instruments DAC3484s to deliver four independent analog outputs each through its own digital up-converter and 16-bit D/A with sampling rates up to 1,25 GHz. A Xilinx Kintex Ultrascale FPGA contains factory-installed functions that include a sophisticated D/A waveform generation IP module. It allows users to easily deliver waveforms stored in either on-board memory or off-board host memory to the four D/As. Complex output waveforms, each with bandwidths up to 250 MHz, can be independently translated to programmable IF frequencies.
“The Jade Model 71871 builds on the capabilities of the popular Jade line of XMCs,” said Robert Sgandurra, director of product management. “Pentek’s Navigator Design Suite adds more IP with each product release, all of which is fully available to our customers for even more effective product development.”
The Model 71871 can be configured with a range of Kintex UltraScale FPGAs to match specific requirements of the processing task, spanning the entry-level KU035 (with 1700 DSP slices) to the high-performance KU115 (with 5520 DSP slices). The KU115 is ideal for demanding beam-forming, modulation, encoding and encryption of the signals prior to transmission. For applications not requiring large DSP resources or logic, a lower-cost FPGA can be installed.
A pair of front-panel μSync connectors allows multiple modules to be synchronised. The Model 71871 can be optionally configured with a P14 PMC connector with 24 pairs of LVDS connections to the FPGA for custom I/O to the carrier board. An optional P16 XMC connector adds an 8X gigabit link to the FPGA to support serial protocols.
The Jade architecture
The Pentek Jade architecture is based on the Xilinx Kintex UltraScale FPGA, which raises digital signal processing (DSP) performance by over 50% over the previous family, with equally impressive reductions in cost, power dissipation and weight.
As the central feature of the Jade architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data unpacking, gating, triggering and memory control. A 5 GB bank of 2400 MHz DDR4 SDRAM provides on-board storage of waveforms for output through the D/As.
Navigator Design Suite for streamlined IP development
Pentek’s Navigator Design Suite was designed from the ground up to work with Pentek’s Jade architecture and Xilinx’s Vivado Design Suite, providing an unparalleled plug-and-play solution to the complex task of IP and control software creation and compatibility. Graphical design entry for Xilinx and Pentek AXI4-compliant IP modules using the Xilinx IP Integrator greatly speeds development tasks.
The Navigator Design Suite consists of two components: Navigator FDK (FPGA Design Kit) for integrating custom IP into Pentek sourced designs, and Navigator BSP (Board Support Package) for creating host applications. Users can work efficiently at the API level for software development and with an intuitive graphical interface for IP design. The Navigator BSP is available for Windows and Linux operating systems.
Designed for air-cooled, conduction-cooled and rugged operating environments, the Model 71871 XMC module comes with 5 GB of DDR4 SDRAM.
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