Programmable Logic

Latest updates to Libero SoC v2021.3 Design Suite

24 November 2021 Programmable Logic

Microchip Technology recently introduced new MPFS025T/095T/160T/250T PolarFire SoC devices with Tgrade2 operating conditions in standard and -1 speed grades and MPFS095TS/250TS/460TS devices with MIL operating conditions in 1,0 V and 1,5 V standard speed grades with Libero SoC v2021.3 Design Suite.

With the version 2021.3 release, Microchip enhanced place-and-route minimum delay repair for external timing closure of IOD interfaces and enhanced XCVR ERM to improve transceiver robustness for PolarFire, RT PolarFire and PolarFire SoC FPGA families of FPGAs. It also introduced export BSDL file support, enabled programming for MPFS250T/TS/TL/TLS and MPFS025T/TS/TL/TLS devices, introduced an option to configure I/O states during JTAG programming, introduced an option to invoke MSS configurator from Libero SoC Design Suite as read-only mode and introduced a device check option when importing MSS components (CXZ) to Libero SoC Design Suite for PolarFire SoC FPGA devices.

With the release of version 2021.3 of SmartHLS, which is embedded in Libero SoC Design Suite v2021.3, IGLOO 2 FPGA family support was added. A new branchless flatten function feature was added to improve parallelism and replicate ROM pragma was introduced to enable and control ROM (array) replication for higher memory bandwidth and improved expression balancing optimisation to reduce cycle latency of generated hardware with the SmartHLS v2021.3 release.

For more information contact Andrew Athanasiou, Altron Arrow, +27 21 555 1884, [email protected],


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