Joint Test Action Group, or JTAG, is the common name for IEEE Standard 1149.1. This standard defines a particular method for testing board-level interconnects, which is also called Boundary Scan. In short, JTAG was created to test for common problems, but lately, it has become a way of configuring devices. The JTAG hardware interprets information from five different signals: TDI (Test Data In), TDO (Test Data Out), TMS (Test Mode Select), TCK (Test Clock), and TRST (Test Report-optional).
The primary advantage of boundary-scan technology is the ability to observe data at the device inputs and control the data at the outputs independently of the application logic. Simple tests can find manufacturing defects such as unconnected pins, missing devices, incorrect or rotated devices on a circuit board, and even failed or dead devices.
The Joint Test Action Group was formed in 1985 to develop a method of verifying designs and testing printed circuit boards after manufacture. In 1990, the Institute of Electrical and Electronics Engineers codified the results of the effort in IEEE Standard 1149.1-1990, entitled “Standard Test Access Port and Boundary-Scan Architecture.” The JTAG standards have been extended by many semiconductor chip manufacturers with specialised variants to provide vendor-specific features.
A JTAG connector is a pin header (that is, a male terminal strip connector), usually on either .100-inch (2,54 mm) or .050-inch (1,27 mm) centreline. Common sizes are 10 pin (2 x 5), 14 pin (2 x 7), and 20 pin (2 x 10). JTAG connectors can be either through hole or SMT, and either shrouded or unshrouded.
If this sounds like quite a loose standard, you would be correct. Actually, there is no single connector standard for JTAG. At the simplest level, a ‘JTAG connector’ only needs four or five pins to operate a JTAG TAP (Test Access Port). However, designers often incorporate ground and signal, and that is where the number of pins increases.
A JTAG TAP is so much more than just a connector with key features of a TAP being:
1. Interface for Boundary Scan Testing – The TAP allows engineers to test interconnections between components on a PCB without requiring physical probes.
2. Debugging and Programming – The TAP provides access to internal registers, memory, and control functions for debugging µCs, FPGAs, and other processors.
3. Serial Communication.
The TAP connects to a JTAG Controller and shifts data into a device’s instruction and data registers through a serial scan mechanism. By shifting in commands, engineers can perform board-level diagnostics, firmware updates, and hardware activation without requiring physical access to the device’s physical pins.
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