Quartus II software version 12.1 bolsters its support for high-level design flows with the inclusion of an SDK for OpenCL and enhancements to both its Qsys system integration tool and DSP Builder model-based design environment.
Also included in the latest software release are several enhancements, such as a partial reconfiguration design flow, new intellectual property (IP) cores and expanded support for 28 nm FPGAs and SoC FPGAs.
The high-level design tools Altera offers include system-level C-based, IP-based and model-based design entry systems. These tools support and simplify the development of today’s advanced programmable systems, which include CPU cores, digital signal processing (DSP) blocks and multiple IP subsystems.
The addition of an SDK for OpenCL allows system developers and programmers familiar with C to quickly and easily develop high-performance, power-efficient FPGA-based applications using an open high-level programming language. The SDK for OpenCL reduces hardware design complexities and allows software programmers familiar with C to target FPGAs.
Enhancements made to Altera’s Qsys system integration tool and DSP Builder tool provide further design productivity and system performance benefits to users.
Qsys features expanded support for industry standard ARM AXI3 and AXI4 protocols, while DSP Builder provides expanded support for seven different floating point precisions, including IEEE 754 half, single and double precision support.
Further simplifying system design, the latest Quartus II software release includes a 100G Interlaken IP core to enable high-speed chip-to-chip packet transfers and a new video trace monitor IP core for video processing applications.
Included in the Quartus II software version 12.1 is the first production release of Altera’s new partial reconfiguration design flow for Stratix V FPGAs. Partial reconfiguration provides the flexibility to change the device’s core functionality on the fly while other portions of the FPGA design are still running.
Designers store different functions in external memory and load them into the FPGA as needed, allowing customers to reduce the size of the FPGA used in their system, save board space and reduce power consumption.
The latest software version also includes a variety of additional enhancements, including support for new devices. Several new 28 nm Stratix V, Arria V and Cyclone V FPGAs and SoC FPGAs are supported in this release, including full support for Arria V GZ FPGAs.
For more information contact EBV Electrolink, +27 (0)21 402 1940, [email protected], www.ebv.com
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