Aldec’s ALINT design analysis and linting tool identifies critical design issues early in the design stage of ASIC and FPGA designs. The tool points out coding style, functional and structural problems in Verilog and VHDL designs, preventing them from spreading to downstream stages of the design flow.
ALINT features a highly customisable and intuitive framework that seamlessly integrates into existing environments and helps to automate any existing design guidelines. Once the design rule checking policy customisation and linting process execution is complete, the user can easily navigate between the violation reports and source code.
The software leverages phase-based linting (PBL) methodology to address the two most common problems with design rule checking tools: an excessive number of reports per session (common, as designs are checked against hundreds of rules) and a high level of ‘noise’ caused by false or irrelevant violations.
User productivity and overall efficiency of the entire linting process can thus be significantly improved as PBL methodology puts clear priorities into the design refinement process and minimises the number of iterations.
ALINT’s extensive design rule libraries are based on best practices, such as STARC and RMM, which have been established over the years by industry-leading companies in FPGA and ASIC design development. Libraries such as Aldec Basic and DO-254 capture the combined knowledge of Aldec customers and in-house design experts.
The majority of rules can be configured based on specific project needs. A C++ based API is also available and allows implementation of fully custom and unique rules.
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