Embedded JTAG translator
3 April 2013
Design Automation
CoreCommander for FPGAs, from JTAG Technologies, offers a generic solution based on VHDL code that allows engineers to bridge from the standard JTAG test and programming port (TAP) to proprietary IP cores (eg, DDR controllers, E-net MAC, USB controllers etc.) and harness them for test purposes. The product is aimed primarily at hardware design and test engineers.
The base of CoreCommander for FPGAs uses a translator block to access proprietary IP cores through commonly implemented bus structures such as ‘Wishbone’, AMBA, Avalon and CoreConnect. This translator block, provided as a VHDL module, can be either permanently or temporarily programmed into a gate array.
Linker software provided with the module automatically links the translator block with IP blocks to build the complete (test) design to be programmed in the FPGA.
Use of CoreCommander functions can be either interactive or ‘automatic’ – via library routines in a scripting environment. The interactive mode is intended for use by design engineers to interrogate and control the IP blocks in their FPGA during debug. The automatic mode, however, is more likely to find favour during (at-speed) logic cluster testing in manufacturing.
Together with interconnect testing, logic device ‘cluster’ testing has been one of the mainstays of JTAG/boundary-scan board testing since its inception over 20 years ago.
However, in recent years the capacity of the simple (low-speed) boundary-scan register (BSR) to cope with sophisticated command and control requirements of parts like DDR memory has diminished to the point that tests can be compromised. By harnessing the horsepower built into devices like microprocessors and now FPGAs, JTAG testing allows the connections to timing sensitive devices to be fully tested and at functional speeds.
For more information visit www.jtag.com
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