Analogue, Mixed Signal, LSI


Clock distribution ICs

29 May 2013 Analogue, Mixed Signal, LSI

ON Semiconductor has released two new clock distribution ICs housed in low-profile 5 x 5 mm 32-pin QFN packages.

Operating from a supply voltage of 2,5 V and 3,3 V, the NB6L56 2:1 clock/data multiplexer’s differential inputs incorporate internal 50 Ω termination resistors. This feature allows the device to accept a broad variety of logic level standards, including low-voltage positive emitter coupled logic (LVPECL), current mode logic (CML) and low-voltage differential signalling (LVDS).

Outputs are 800 mV ECL signals. The additive clock and data jitter produced is minimal even when operating at 2,5 GHz and 2,5 Gbps rates respectively. This makes the NB6L56 highly optimised for use in SONET, Gigabit Ethernet and Fibre Channel network infrastructure, as well as other telecom and data communication applications.

The NB3F8L3010C is a 3:1 multiplexer and a 1:10 clock/data fanout buffer targeted at networking and communications applications. Operating from a 3,3 V or 2,5 V core supply, it has differential inputs which accept LVPECL, LVDS, host clock signal level (HCSL) and stub series terminated logic (SSTL) signals. The IC has a total of 10 single-ended LVCMOS outputs, each capable of running at 200 MHz. Output skew is typically kept to just 10 ps.



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