JESD204B FPGA debug software
19 February 2014
Design Automation
Analog Devices has revealed an FPGA-based reference design with software and HDL code that reduces the design risk of high-speed systems incorporating JESD204B-compatible converters.
Called the JESD204B Xilinx Transceiver Debug Tool, it supports the 312,5 Mbps to 12,5 Gbps JESD204B data converter-to-FPGA serial data interface and Xilinx 7 series FPGAs and Zynq-7000 All Programmable SoCs. It is available at no cost with ADI converters and provides an on-chip, 2D statistical eyescan that helps designers of radar arrays, software-defined radio and other high-speed systems more quickly verify the signal integrity of JESD204B data converter-to-FPGA designs using gigabit transceivers.
The tool provides on-chip eyescanning that augments the test and measurement process by statistically determining signal integrity inside the FPGA. Where other techniques probe the outside of the FPGA package and acquire the signal before it’s been processed by Xilinx’s automatic gain control and equaliser blocks, this approach yields a more accurate result by utilising the Xilinx transceiver on-chip eyescan feature to allow developers to monitor the signal integrity and design margin on their JESD204B links inside the FPGA.
Analog Devices’ reference design gathers data directly from the on-chip Rx margin analysis feature in the 7 series IBERT core and manages the data locally inside the FPGA or one of the ARM dual-core Cortex-A9 MPCore processors, displaying the data on an HDMI monitor or over Ethernet to a remote monitoring station.
For more information contact Erich Nast, Avnet Kopp, +27 (0)11 319 8600, [email protected], www.avnet.co.za
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