Xilinx is touting acceleration of system verification with the release of Vivado Design Suite 2015.1, featuring major productivity advances for the development and deployment of its ‘All Programmable’ FPGAs and SoCs. This release includes the Vivado Lab Edition, accelerated Vivado Simulator and third party simulation flows, interactive clock domain crossing (CDC) analysis, and advanced system performance analysis with the Xilinx Software Development Kit (SDK).
The Vivado Lab Edition is a no-cost, lightweight programming and debug edition of the Vivado Design Suite. It includes the Vivado Device Programmer, Vivado Logic and Serial I/O Analyser, as well as memory debug tools, and is intended for use in lab environments where the full-featured Vivado Design Suite is not required.
Lab Edition is 75% smaller than the complete version, which considerably reduces lab setup time and system memory requirements. For design teams that require remote debug or programming over Ethernet, a standalone hardware server is provided, which is less than 1% of the complete edition.
Vivado Design Suite 2015.1 also features advancements in the simulation flows that reduce the LogiCORE IP compile times by over two times. As a result, overall simulation performance is 20% faster compared to previous releases. The release also includes fully integrated simulation flows with Alliance Program members Aldec, Cadence Design Systems, Mentor Graphics and Synopsys.
Xilinx has also extended its advanced verification portfolio by offering an interactive CDC analysis capability. This feature improves productivity by enabling the debug of CDC issues earlier in the design, reducing expensive in-system debug cycles. Combined with the software’s interactive timing analysis and cross-probing features, the CDC analysis capability provides powerful timing analysis and debug functionalities.
To accelerate the development of the Zynq-7000 All Programmable SoC, Xilinx has extended its system performance and analysis toolbox for bare metal and Linux applications. The Xilinx SDK now provides embedded software developers the ability to analyse the performance and the bandwidth of their SoC design, including key performance metrics for the processor subsystem (PS) as well as bandwidth analysis between the PS, the programmable logic (PL) and external memories. System modelling designs using AXI traffic generators are provided for the ZC702 and ZC706 evaluation boards.
For more information contact Erich Nast, Avnet South Africa, +27 (0)11 319 8600, erich.nast@avnet.eu, www.avnet.co.za
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