Computer/Embedded Technology


RFSoC board for radar and DRFM

13 June 2018 Computer/Embedded Technology

Pentek introduced its first product in the Quartz architecture family, the Model 5950 – an eight-channel A/D and D/A converter, 3U OpenVPX board based on the Xilinx Zynq UltraScale+ RFSoC FPGA. The low latency benefits of the architecture support DRFM (digital RF memory) and radar applications that were previously not possible with earlier generation products.

Designed to work with Pentek’s Navigator Design Suite tools, the combination of Quartz and Navigator offers users an efficient path to developing and deploying FPGA software and IP for data and signal processing. The Xilinx Zynq UltraScale+ RFSoC Processor integrates 8 RF-class A/D and D/A converters into the Zynq FPGA fabric and quad ARM Cortex-A53 and dual ARM Cortex-R5 processors, creating a multichannel data conversion and processing solution on a single chip.

Complementing the RFSoC’s on-chip resources, the Quartz board architecture adds:

18 Gb of DDR4 SDRAM; sophisticated clocking for single-board and multi-board synchronisation; high signal-integrity connectors for RF inputs and outputs; x8 PCIe Gen 3 link; an 8 lane, 28 Gbps optical interface supporting a built-in dual 100 GigE interface or customer installed protocols; 12 LVDS general purpose I/O pairs for specialised interfaces; QuartzXM eXpress module design for flexible development and deployment; and factory-installed application IP.

The Model 5950 is pre-loaded with a suite of Pentek IP modules to provide data capture and processing solutions for many common applications. Modules include DMA engines, DDR4 memory controller, test signal and metadata generators, data packing and flow control.

The board can be used out-of-the-box with the built-in functions requiring no FPGA development. It comes pre-installed with IP for DFRM, triggered waveform and radar chirp generator, triggered radar range gate engine, wideband real-time transient capture, flexible multi-mode data acquisition and extended decimation.

Technical specifications

The front end accepts analog IF or RF inputs on eight front panel MMCX connectors with transformer-coupling to eight 4 GSps 12-bit A/D converters delivering either real or complex DDC samples. With additional IP-based decimation filters, the overall DDC decimation is programmable from 2 to 128.

The eight D/A converters accept baseband real or complex data streams from the FPGA’s programmable logic. Each 6,4 GSps 14-bit D/A includes a digital up-converter with independent tuning and interpolations of 1x, 2x, 4x and 8x. Each D/A output is transformer-coupled to a front panel MMCX connector.

The Model 5950 supports the VITA-66.4 standard providing eight 28 Gbps duplex optical lanes to the backplane. With two built-in 100 GigE UDP interfaces or a user-installed serial protocol, the VITA-66.4 interface enables gigabit communications independent of the PCIe interface.

Streamlined IP development

Pentek’s Navigator Design Suite includes the Navigator FDK (FPGA design kit) for custom IP and Navigator BSP (board support package) for creating host software applications.

The Navigator FDK includes the board’s entire FPGA design as a block diagram that can be edited in Xilinx’s Vivado tool suite; all source code and complete documentation is included. Developers can integrate their IP along with the factory-installed functions or use the Navigator kit to replace the IP with their own. The Navigator FDK Library is AXI-4 compliant, providing a well-defined interface for developing custom IP or integrating IP from other sources.

The Navigator BSP supports Xilinx’s PetaLinux on the ARM processors. Users work efficiently using high-level API functions, or gain full access to the underlying libraries including source code. Pentek provides numerous examples to assist in the development of new applications.

With a 3U VPX SPARK, development systems are ready for immediate operation with software and hardware installed. In many applications, the SPARK development system can become the final deployed application platform.



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