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Electronics Buyers' Guide

Electronics Manufacturing & Production Handbook 2019


 

Dual- and single-core DSCs
29 May 2019, DSP, Micros & Memory

New dual- and single-core dsPIC33C digital signal controllers (DSCs) have been released by Microchip Technology, with more options to meet changing application requirements across memory, temperature and functional safety.

The aim is to help system developers to design high-end embedded control applications which need flexible options to provide scalability as projects increase in complexity.

The new dsPIC33CH512MP508 enables support for applications with larger program memory requirements, while the dsPIC33CK64MP105 single-core DSC adds a cost-optimised version for applications that require smaller memory and footprint. Developers can scale across product lines using the new devices, which are pin-to-pin compatible within the dsPIC33CH and dsPIC33CK families.

The dsPIC33CH512MP508 (MP5) family expands the recently introduced dsPIC33CH, with Flash memory growing from 128 KB to 512 KB, and triples the program RAM from 24 KB to 72 KB. This enables support for larger applications with multiple software stacks or larger program memory, such as automotive and wireless charging applications.

More memory is needed to accommodate AUTOSAR software, MCAL drivers and CAN FD peripherals in automotive applications. Implementing wireless charging in automotive applications requires additional software stacks for the Qi protocol and near-field communication (NFC), driving the need for even more program memory.

Using Live Update capability for real-time firmware updates is essential for high-availability systems but also doubles the overall memory requirement. In the dual-core devices, one core can function as a master while the other is designed as a slave. The slave core is useful for executing dedicated, time-critical control code while the master core is busy running the user interface, system monitoring and communications functions.

For example, having two cores facilitates partitioning of the software stacks for parallel execution of the Qi protocol and other functions such as NFC to optimise performance in automotive wireless charging applications.

The dsPIC33CK64MP105 (MP1) family extends the recently introduced dsPIC33CK family with a cost-optimised version for smaller memory and footprint applications, offering up to 64 KB Flash memory and 28- to 48- pin packages. Package sizes are available as small as 4 x 4 mm. This compact device offers a beneficial combination of features for automotive sensors, motor control, high-density DC-DC applications or standalone Qi transmitters.

Both single- and dual-core dsPIC33C devices enable fast deterministic performance for time-critical control applications, providing expanded context selected registers to reduce interrupt latency and bringing faster instruction execution of math-intensive algorithms.

All devices in the dsPIC33C family include a fully featured set of functional safety hardware to ease ASIL-B and ASIL-C certifications in safety-critical applications. Functional safety features include multiple redundant clock sources, fail-safe clock monitor (FSCM), I/O ports read-back, Flash error correction code (ECC), RAM built-in self-test (BIST), write protection, analog peripheral redundancies and more. A robust set of CAN-FD peripherals, together with the new support for 150°C operation, make these devices well suited for use in extreme operating conditions such as under-the-hood automotive applications.

For more information contact Shane Padayachee, Avnet South Africa, +27 11 319 8600, shane.padayachee@avnet.eu, www.avnet.co.za


Credit(s)
Supplied By: Avnet South Africa
Tel: +27 11 319 8600
Fax: +27 11 319 8650
Email: sales@avnet.co.za
www: www.avnet.co.za
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