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Benefits of lightning-fast timing analysis
28 August 2002, News

ASIC designers heavily use timing analysis as both a form of debugging their ASIC design and using it in conjunction with a synthesis tool to properly constrain the design for synthesis. In addition, the same timing analysis engine used to analyse results post-synthesis is often the timing engine used within the synthesis engine for making the right optimisation decisions. Here we will explore the importance of very fast runtime in enabling designers to achieve high design productivity in their flow and look at examples of how a fast, integrated timing engine can allow designers to come to design closure quickly. Design flow graphics are included in this article.

ASIC designers heavily use timing analysis as both a form of debugging their ASIC design and using it in conjunction with a synthesis tool to properly constrain the design for synthesis. In addition, the same timing analysis engine used to analyse results post­synthesis is often the timing engine used within the synthesis engine for making the right optimisation decisions. Here we will explore the importance of very fast runtimes in enabling designers to achieve high design productivity in their flow and look at examples of how a fast, integrated timing engine can allow designers to come to design closure quickly. Design flow graphics are included in this article.

In noting where the timing engine fits in, look at Figure 1 which shows the typical synthesis flow. It is important to see that the timing engine is present in two distinct places of the diagram: (1) In conjunction with the mapper as it attempts to meet the specified timing constraints; (2) In the final step as it creates a timing report and identifies the critical paths.

Figure 1. Timing engine within the synthesis flow
Figure 1. Timing engine within the synthesis flow

Timing engine in conjunction with the mapper

While most ASIC designers regard a timing analyser as being a back-end tool that is run a few times only after a design is fully synthesized, many fail to realise that it is also embedded in the heart of the synthesis flow. It is in here that a lightning fast timing engine, coupled with an efficient mapper, is critical in achieving very fast synthesis run times. To understand this better, consider the diagram in Figure 2.

Figure 2. Breakdown of the synthesis flow into its major constituents
Figure 2. Breakdown of the synthesis flow into its major constituents

The diagram shows that the synthesis flow is comprised of two phases: compiling and mapping/timing. Historically, the mapping/timing phase has been the bottleneck. To improve the efficiency, developers have come up with a timing engine that operates in incremental mode. Such a mode requires updating only the timing information that was affected by optimisations in the mapper. Since this is the most common case, the result is a much faster timing engine. Improving the performance of the timing engine yields the following benefits:

* Permits the mapper to try out more permutations of possible design structures and optimisations within the same out of time, thereby yielding a more thorough analysis of the design.

* Provides the ASIC designers with faster feedback. This allows them to experiment with different design structures and fix more timing violations within the same amount of time.

Both these benefits imply better QoR and a shorter time to market. In addition, these benefits are exhibited not only in the initial synthesis run, but also in further iterations and synthesis optimisations.

Timing engine as a report generator

The speed of the timing engine is still a factor here. A slow timing engine may, for example, hinder the user from asking for a large number of paths. Instead of asking for the 30 worst violations, a user may be tempted to request the 10 worst ones, fix those, and then see what the next 10 worst ones are. That process would require two extra cycles that otherwise would have been unnecessary.

Nonetheless, the speed of the timing engine is now overshadowed by its ability to provide the designer with useful information quickly. The critical factor now becomes how well the timing analyser is integrated into the synthesis flow and how quickly the user interface can translate the results of the timing report into meaningful information for the designers. Rather than burden them with writing short scripts that search for keywords inside the timing reports, having a sophisticated, user-friendly GUI that crossprobes the critical paths back to the original HDL code and/or gate level netlist would be key in helping the designer to quickly and efficiently: identify the critical paths, visualise the logic blocks they traverse, and, grasp any redesigning or repartitioning tasks that need to be undertaken to fix the violations.

Synplify ASIC software

The Synplify ASIC solution has an embedded timing engine identical to the one used in Synplicity's FPGA synthesis products. It is designed and optimised for incremental mode. This is in line with one of the most fundamental rules in computer architecture: make the common case fast. Thus, with this design, Synplify ASIC software has eliminated a huge bottleneck in the synthesis flow, and created one of the fastest and most accurate timing engines. This translates directly into a much faster synthesis engine and explains why the Synplify ASIC solution can boast extremely fast runtimes.

In addition, the GUI features of the HDL Analyst environment are tightly integrated into the Synplify ASIC synthesis tool. This equips the designer with two extremely useful views: the RTL view and the technology view. These views allow the designer to crossprobe any timing violations or critical paths back to the RTL code or gate-level netlist respectively, thereby serving as quick, intuitive tools that replace an archaic and inefficient form of debugging.

Conclusion

In attempting to quantify the increase in productivity, it can be shown that by considering the application of the synthesis engine to various aspects of the development cycle - such as, design and exploration; spec changes; and, the synthesis-timing optimisation loop - it is conceivable that the Synplify ASIC solution can shave off a month on a design that typically required an eight month cycle from concept to tape-out. This is equivalent to a 12,5% faster time to market. Given that most of the profits are made right after the product hits the market and before competitors have jumped in, the net gains from choosing the right synthesis engine can be huge.

The Synplify ASIC solution is designed with a lightning fast timing engine that is tightly integrated into the synthesis flow enabling the ASIC designer to not only experiment and iterate quickly on his design, but also to crossprobe critical paths back to the source code and glean a more thorough understanding of the violations faster.


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