Altera has announced an innovative technique for increasing the DSP capability of its FPGAs by building fast, flexible multipliers out of on-chip memory. Using a patented technique for creating 'soft' multipliers from Stratix TriMatrix memory structures, the number of high-performance multipliers in a Stratix FPGA can be increased up to 500% it claims.
Soft multipliers are ideal for multichannel applications as well as multiplier- intensive functions common in communications applications such as echo cancellers, equalisers, multi-user detection, and beam forming. "Soft multiplier technology made Stratix FPGAs the best fit for our fixed broadband wireless application," said John Federkins, director of engineering at CoWave Networks. "... we determined that our fast-fourier transform would benefit most from the greater amount of on-board memory and soft multiplier flexibility available with Stratix FPGAs."
Soft multipliers are equal in performance to the existing embedded or 'hard' multipliers provided by on-chip Stratix DSP blocks says Altera. DSP designers can use soft multipliers to augment hard multipliers. The largest Stratix FPGA, the EP1S120, offers 112 18x18 multipliers capable of running at 300 MHz via the DSP blocks. Using soft multipliers increases this quantity to 612, three times the maximum number offered by other FPGA vendors claims the company. In addition, soft multipliers can efficiently implement multiplier sizes that are resource-inefficient in hard multipliers, such as asymmetric multipliers or multipliers that are not easily scaled up from the hard multiplier configuration.
"In addition to fast, true-dual port memory access, Stratix TriMatrix memory blocks now deliver unprecedented multiplier performance, flexibility, and efficiency," noted Justin Cowling, director of Altera's IP marketing. "Soft multipliers provide DSP designers with options and performance levels that are not available with any other DSP device offering, significantly increasing the value of Altera's reconfigurable DSP solution."
For more detailed information on how to use soft multipliers in Stratix FPGAs, readers can download Application Note 246: 'Using soft multipliers with Stratix devices' at www.altera.com/literature/lit-an.html?xy =001_1.
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