Circuit & System Protection


EMC design practices: ESD is shocking experience for electronics

26 Jan 2000 Circuit & System Protection

Do not shrug off that little zap as a mere annoyance.That is ESD and a killer if you do not take steps to prevent it in your EMC designs.

Zap! Your CMOS device is dead - and you did not even feel it. All you know is that after you reassembled your system, it booted to the dreaded blue screen with a cryptic message that translates to: It is dead. No wonder. It only takes 50 to 250 V to fry FETs, CMOS and other low-noise, wide-bandwidth, static-sensitive devices, but it takes 1500 V or so before we humans can feel the discharge.

ESD comes in all amplitudes, but a simple worst-case model for a human body discharge is a single 35 kV, 75 A sawtooth with a 2 ns rise time and an 8 ns fall time. A great big ouch - nearly impossible to achieve with human body charging. But it does help us acquire a feeling for the magnitude of the problem.

Even so, this transient is not nearly as big as can be developed from carts, furniture and moving parts. ESD is a formidable problem that usually ends with the destruction of sensitive semiconductor devices unless the system is carefully designed to divert the short duration, 2 µW to 3 MW surge away from them. Even then, without additional protection, we still can expect some systems to respond to the transient radiated electric fields (EF) and magnetic fields (HF).

Probably the only good thing about ESD is that it makes a great way to evaluate the electromagnetic susceptibility/immunity design of a system. If the system continues to operate during and after ESD testing, then it probably will withstand almost anything. Charge development is very interesting. Many of us observed the phenomenon in a physics class. Remember rubbing the glass rod with cat fur and the hard rubber rod with wool to create positive and negative charges? Others experience ESD during the dry winter months when they walk across the nylon carpet, reach for the door handle and are shocked.

Charge transfer and accumulation occur between nonconductive materials (>109 y/sq) when they are brought into intimate contact and then separated. As a result, ESD problems are created primarily by rubbing, sliding and rolling or rubber, paper, textiles, plastics, leather, people, dry powders and gases.

Since electrons have a negative charge, an accumulation of electrons is a negatively charged body while the loss of electrons is a positively charged body. Polarity is determined by the relationship of the contact materials and magnitude is limited principally by the surrounding relative humidity. Because charge accumulation is so closely linked to humidity, maintaining a relative humidity greater than 50% will minimise ESD problems even under the worst conditions.

When a charged body is brought close to another charged or neutral body, especially if the neutral body is grounded, recombination of charges neutralises or equalises the charge and results in very high rates of current flow (di/dt). When equalisation of charge occurs, both bodies still are charged and discharge can occur between these bodies and other bodies with different or neutral charge potential.

ESD-coupled failures range from temporary to major disasters. The major disasters are caused by direct-current injection into semiconductor devices. These hard, permanent failures are the result of junction burnout or shorts, dielectric breakdown and metallisation melt.

The failures depend on how the devices are constructed and if they have internal protection diodes. For example, 90% of bipolar failures are due to junction burnout and shorts and 10% from metallisation melt. With MOS failures, 63% are from metallisation melt and 27% from dielectric breakdown. These failures are permanent so it is extremely important that devices be protected from direct-current injection.

Soft failures usually are recoverable and caused by the radiated EFs and HFs or the electrostatic field. A nearby electrostatic field causes a small internal charging current to flow, polarises the material and maintains an EF gradient while it is present. Typically, this is not a problem.

On the other hand, radiated transient EFs and HFs created by the ESD current most definitely are a problem. The EF strength can reach values of 200 V/m with all frequencies present. There are no harmonics. Consequently, it does not matter if the system has resonant circuits because high-level ESD-generated EFs will exist at the tuned frequency of the circuits. These typically are coupled as common-mode.

Even though ESD problems are largely magnetic, the radiated HF is somewhat less of a problem because its intensity decreases rapidly with separation distance from the ESD current path. Since HFs are coupled into loops, the HF coupling is more likely to be differential-mode. In both cases, the energy coupled into resonance circuits increases with increasing bandwidth. Figure 1 illustrates these various ESD coupling mechanisms.

Systems must be designed to withstand ESD events. The ESD environment is so severe that we cannot trust it to luck. Plus, equipment being shipped to Europe and other countries must meet ESD limits based on operational requirements. Even if there is no legal requirement, there is a design obligation to meet some minimum ESD limit to facilitate reliable operation of the system. It is a lot easier to sell a system that works everywhere throughout the year.

Fortunately, some of the most important protection methods are free if they are designed in and not retrofitted to a nonfunctional design. The following discussion summarises the five most important design categories for ESD protection: segregation/isolation, PCB/electronics design, cable design, filtering and shielding.

Segregation/isolation

All metallic areas that the operator can touch should be grounded and the ground should be routed away from the electronics. Spacing is important. To protect semiconductor materials from direct-current injection and reduce the coupled HFs, provide at least a 2,2 mm separation for uninsulated ground traces or wires and 20 mm (20 kV) for uninsulated electronics.

PCB/electronics design

Because the voltage induced into a coupling loop is a function of the frequency, loop area and circuit bandwidth. Keep wide-bandwidth loop areas small. Amplitude or bandwidth protect sensitive inputs with transient protectors, filters, ferrites and capacitors. Do not have floating inputs.

Cable design

Shield cables to sensitive circuits. Ground cable shields using high frequency techniques. Use high-quality shielded connectors with the shield terminated on the outside of the equipment enclosure. Do not use pigtails. Running a cable shield through a connector pin and attaching the shield to ground inside the enclosure creates a pigtail. And do not route cable shield grounds to the PCB.

Filtering

Critical leads should have transient protection and the filters should be placed at the end closest to the sensitive device. If filter capacitors are used they should be wide bandwidth and able to withstand the ESD transient amplitude. Bandwidth is a function of both the dielectric material and lead inductance. Generally, a good choice is a 1 kV ceramic capacitor. Do not filter the ESD current path.

Enclosures/shielding

Plastic enclosures with no exposed metallic areas were thought to be the solution to the ESD problem and they do a great job of isolating the electronics from direct-current injection and preventing direct EF/HF radiation. After all, no current - no radiation. Unfortunately, they do not provide isolation from indirect radiated EF/HF.

Circuits and equipment sensitive to indirect radiation must be shielded. Overlap seams. Apertures should be smaller than 20 mm and spaced more than 20 mm apart. Ground exposed metallic panels. Bonding resistance should be less than 2,5 mOhm.

Conclusion

ESD transients are very severe with high energy levels at frequencies up to about 300 MHz. Consequently, ESD testing can be used as an engineering susceptibility test to verify PCB layout (loop areas, decoupling capacitors and grounding), I/O port/cable pick-up, filter installation and shield integrity.

Testing is performed by dividing the equipment into zones and applying lower-level ESD pulses to metal panels, screws, devices, cables and seams within each zone and recording operational disruptions. If the enclosure is plastic, an indirect test is performed on the system by placing a grounded metal panel adjacent to its plastic enclosure and applying ESD to it.

After all zones have been checked, the ESD level is increased by 1 kV and the test is repeated. Then the failure data is analysed and fixes are incorporated starting with the weakest area. The test and analysis cycle is repeated until the required ESD objective has been met.

The equipment should meet the EU ESD test criteria called out in EN 61000-4-2, the de facto international ESD standard. Incidentally, ESD compliance testing often is performed only once with the ESD levels set to the required pass/fail level. If the test is performed this way and the device passes, great. If it fails, then the testing usually is finished until repairs can be made.

Just as a suggestion, perform the compliance test in much the same way as an engineering test. Then if it fails, there will be some data to aid in the repair process.





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