Increasingly, fast microprocessors cause coupling, crosstalk, EMI and signal integrity dilemmas in today's PCB designs. The speed of today's logic devices mandates that the interconnects on PCBs must meet the high switching rise/fall times of these devices. Switching edges are now in the 200 ps to 300 ps range and some devices have edges that have broken the 50 ps barrier. This has resulted in high-speed board design problems such as: a lack of control over impedance and reflections; crosstalk and bypassing failures; time delays, false triggering and reflections; and subsequent failure to meet EMI and FCC requirements.
EDA Technologies has brought renowned design expert, Robert Hanson to South Africa to deliver two seminars. The first seminar on the 14-16 April is 'SMT manufacturing and test', and the second on 19-22 April is 'High frequency digital design'.
The explosive growth of high-density SMT packaging has had a major impact on companies that design and manufacture electronic equipment. As market pressures make it necessary for designers to pack more features into smaller volumes, they strongly influence choices of IC package style, PCB design, material selection and manufacturing processes. The SMT manufacturing and test course was designed to explain SMT design and manufacturing principles, while confronting the technical and economic issues that accompany the choice of a design/packaging approach such as:
* Can I assemble and test high-density SMT assemblies with my current manufacturing equipment?
* Are my soldering process capabilities compatible with the requirements of these new SMT device packages?
* What happens to in-line PCB inspection if the solder joints are not visually accessible?
* How can I maintain adequate control of my product performance and quality if I use the services of a contract manufacturer?
The step-by-step instructional approach explains major facets of SMT manufacturing from board fabrication through assembly line processes. The information presented provides the technical background and practical insights into what works and what does not work in designing and manufacturing electronic assemblies.
In the High frequency digital design seminar, which includes PCB layout and EMI-EMC issues, engineers and designers are shown how to properly design with CAE and CAD. This includes designing to control clock loading and eliminate transmission line effects, to select the tool set to ease the design process, and to describe the issues of the PCB (stack up, laminate choice, and embedded components).
Since it is the edge rate, not the frequency, that causes high-speed problems, even moderate frequency designs can reflect high-speed effects. Many designs today use a microprocessor and modern micros have clock rates around 400 times higher than the original 8 and 16 bit machines. A key factor is the minimisation of the semiconductor device (now at 0,15 µm) leading to less parasitic L and C and thereby faster switching rates. This phenomenon is also apparent in RAMs, ROMs, ASICs and gate arrays. This leads to PCBs requiring terminators, new CAD routing disciplines, and component additions to minimise ground bounce effects.
The purpose of this seminar is to provide designers with the knowledge to do it right the first time. The seminar provides tools for recognising the problems with any proposed high-speed design. Design rules and design processes are taught that ensure the PCB will function properly at the prototype stage. The course emphasises cost competitive design without sacrificing high-speed integrity.
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