The key is ... nothing
13 June 2007
News
Information from Frost & Sullivan Technical Insights
By making use of an innovative technique, researchers at IBM have been able to surround copper wires within electronic chips with an insulating vacuum - an advance that should lead to more efficient processors. The patented approach, which the researchers call 'airgap', is currently integrated into one IBM production facility. The company says that the technology should be in use in all its production lines by 2009, and will be integrated into chips at the 32 nm node.
Rather than using a photolithographic approach to create the structures, the IBM team made use of self-assembly, a technique being eagerly explored by nanotechnology researchers. In the technique, chemical or structural properties found in molecules or structures are used to encourage the materials to order themselves into patterns.
Empty space between the microprocessor’s wiring
"This is the first time anyone has proven the ability to synthesise mass quantities of these self-assembled polymers and integrate them into an existing manufacturing process with great yield results," said Dan Edelstein, one of the researchers on the project. A mix of polymers is poured onto a chip and then baked, yielding a pattern of tiny holes. The glass coating on the wires is etched away, and another layer of glass is applied over the top of the hole-riddled polymer in a vacuum chamber, sealing off the holes, and leaving vacuum-filled chambers inside.
Normally, the tiny wires in a microchip are separated by an insulating material to prevent interference between wires. However, as chip feature sizes continue to scale downwards, finding high-quality insulating layers with the right electronic properties is becoming more difficult, and current leakage due to capacitance issues - which in turn leads to unwanted heat - is becoming more of a problem. Replacing the insulating material with a vacuum, Edelstein said, allows for better performance than would be possible with equally sized amounts of conventional materials. He estimated that using the approach, it should be possible to boost chip speeds by 35% compared to conventional methods, or to reduce power consumption by 15%.
For more information contact Frost & Sullivan Technical Insights, +27 (0)21 680 3274, patrick.carins@frost.com
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