Electronic devices such as mobile phones, portable music players and video players, have become more powerful and more versatile with each passing year.
This trend is expected to continue, as researchers try to pack more capabilities and advanced features into these devices, while simultaneously trying to make them more compact.
However, a major drawback with this approach is that, as more computationally intensive algorithms and advanced signal processing capabilities are embedded onto these devices, the processing chips not only need to operate at higher speeds, but also consume more energy. In other words, the faster a processor works, the more it heats up. Consumers will invariably be less interested in an electronic device that requires frequent battery recharging, however advanced the features it is able to offer.
In an attempt to meet these challenges, researchers from the University of California have developed a highly energy efficient digital signal processing (DSP) chip that also offers very high speeds for common computing tasks. The novel chip reportedly consumes such little energy that it enables a battery powering it to last up to 75 times longer, when compared to contemporary DSP chips. The chip has a maximum clock speed of 1,2 GHz, but when used at slower speeds, offers significantly higher energy efficiency rates. The work is described in a recent paper published in the IEEE Journal of Solid State Circuits.
The processor, tentatively dubbed asynchronous array of simple processors (AsAP), consists of an array of 167 simple programmable processors. The computational platform is capable of per-processor dynamic supply voltage and clock frequency scaling. Besides these, the chip also consists of three algorithm-specific processors and three 16 KB shared memories.
This entire setup is implemented in 65 nm complementary metal oxide semiconductor (CMOS) and all processors and memories are clocked by fully independent, digitally programmable oscillators. At 1,2 V, the processors operate at 1,07 GHz and consume 47,5 mW, which results in an energy dissipation as low as 44 pJ per operation. Likewise, at 0,675 V, they operate at 66 MHz, consuming 608 μW, and consequently dissipating energy as low as 9,2 pJ per operation. This ostensibly means that 93 AsAP chips could achieve 1 Tera-operations (1012) per second while consuming only 9,2 W.
This radical architecture represents one of the highest clock-rate processor chips designed at any university. It is believed that the novel chip could pave the way for the next generation of compact, superfast, and yet, ultra energy efficient electronic devices.
Despite the novel architectural and circuit features, the chip is built with industry-standard fabrication technology and design tools, consequently enabling easy manufacturing using existing equipment. The AsAP is fully reprogrammable and highly configurable, and as a result, can be widely adapted to a range of applications.
Besides applications in portable electronic devices, the AsAP chip is also highly applicable for specialised devices such as anti-lock brakes, ultrasound and medical imaging machines. The compactness of the chip makes it ideal for applications requiring extreme miniaturisation that are consequently very sensitive to energy requirements, such as retinal implants and hearing aids.
The researchers have also written numerous software applications for the chip, including a fully compliant Wi-Fi transmitter and receiver, besides several complex components of the H.264 video encoder.
For more information contact Patrick Cairns, Frost & Sullivan, +27 (0)21 680 3274, [email protected], www.frost.com
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