A team of researchers from Stanford University has developed three-dimensional (3D) carbon nanotube circuits for the first time.
These novel circuits are expected to enhance the speed of computing and thereby reduce their power consumption. Developing carbon nanotube circuit-based computers could realistically take another 10 years, but the Stanford team has developed a method to manufacture stacked circuits using carbon nanotubes. These circuits also have the capability to cram more power in a defined area, thereby dissipating waste heat.
A recent study performed by the team of researchers at IBM’s Watson Research Centre showed that, for a given total power consumption, the circuit developed from carbon nanotubes is five times faster than that of conventional silicon chips. Traditionally used silicon chips can be miniaturised, but at the same time, the desired performance from the silicon chips is not achieved. There is therefore a need for an alternate material that can be used to miniaturise the circuits and at the same time maintain device performance.
In the past, researchers have achieved success in developing carbon nanotube-based transistors, but scaling them onto the circuits has been a challenge. This challenge could possibly be overcome by the methodology developed by the team at Stanford. Using this methodology, it might be possible to develop complex nanotube circuits, despite the limitations posed by the fabrication material.
Initially the team at Stanford grew arrays of nanotubes on quartz substrate to manufacture circuits. Some nanotubes grew in straight lines while a few of them in a crooked manner. A team of chemists was appointed to work on methods that can be used to grow nanotubes in a straight line. The grown nanotubes contained both semiconducting and metallic nanotubes.
Further, the team developed a method to manufacture circuits using metallic carbon nanotubes using a ‘dumb’ layout. A stamp was used to transfer the flat lying aligned carbon nanotube arrays on to a silicon wafer. Further metal electrodes were placed above the nanotubes. An insulating layer that acts as a back gate was placed in between the silicon and the nanotubes. This allowed the researchers to switch off the semiconducting nanotubes before using the metal electrodes to burn out the metallic nanotubes with a blast of electricity. A top gate is added in such a way that it does not connect with any of the misaligned nanotubes. The metal electrodes are removed by etching, as they are not required for the final circuit.
Further, to develop a 3D nanotube circuit, the team repeated the stamping and electrode growth process to stack the required number of layers before the etching process. The process demonstrated by the team is a novel way of stacking as many layers as possible, as it is performed at a low temperature that does not melt the metal electrical contact under the layers. Until now the team has fabricated nanotube arrays of 10 nanotubes per micrometre. To avail a better performance, the team is working on methods to fabricate 100 nanotubes per micrometre. The team is also working on methods for developing complex integrated circuits.
For more information contact Patrick Cairns, Frost & Sullivan, +27 (0)18 464 2402, patrick.cairns@frost.com, www.frost.com
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