Rapid evolution in lithography processes and front-end processes have allowed the semiconductor industry to uphold Moore’s Law, with transistor density doubling every 18 months. The doubling of transistors drives the development of faster microprocessors and denser memory blocks in chips. Recent developments pushing circuit sizes to physical limits have however encountered reliability issues relating to front-end processes. Such defects include bias temperature instability (BTI), hot carrier injection (HCI) and time dependent dielectric breakdown (TDDB).
Researchers from the University of Minnesota have detailed the possible means of on-chip testing technologies in addressing time-dependent device degradation. In their research, BTI, HCI and TDDB defects were addressed, with methodologies capable of differentiating effects of each defect type. According to the researchers, the goal of an on-chip testing system addressing degradation should include capabilities of being able to characterise different ageing mechanisms, performing sensitivity analysis under stressed conditions and require a small spatial overhead. By inclusion of on-chip test circuitries, testing can be performed with improved timing control and resolution, which could not be achieved by the use of external test systems.
The team proposed a ring oscillator comparison methodology for the identification of BTI and HCI defects. Defect identification is done by comparing a stressed ring oscillator to another similarly stressed reference ring oscillator, with a stressed ring showing signs of decreased frequency. According to the authors, failure detection resolution is very high, up to 0,01% within 0,3 microseconds of measurement time. Characterisation of failures between BTI and HCI requires the subtraction of BTI components. As for TDDB, a statistical approach is required incorporating Weibull’s distribution, with the aid of transistor arrays for parallel data collection. The researchers however do not foresee on-chip detection of TDDB being used to control countermeasures used in device control. For example, operating frequency of a device can be reduced to compensate ageing of the device.
The current approach of semiconductor companies in addressing time-dependent failures is to reduce operating conditions of devices. By doing so, it is hoped that the devices will operate ‘normally’ throughout their lifespan, even in the presence of degradation. For instance, frequency of clocks is reduced, in anticipation of frequency reduction caused by device degradation. In effect, spatial reduction in circuit geometry has not been made use of. Going deeper into the sub-micrometre region every other year, this approach might not be sufficient. As such, significant resources have been allocated to understanding the ageing effect in semiconductor devices. As for whether the technology would replace device probing (testing for defects at wafer level), the researchers believe on-chip analysis could validate probing results but is unlikely to replace probing entirely.
Conformance with Moore’s Law has put great pressure on the semiconductor industry in terms of research. In particular, there are difficulties in front-end technologies in matching the rate of miniaturisation. In such a scenario, similar testing improvements will be required to identify emerging forms of defect related to downsizing of chips. On-chip fault detection circuitry serves both as a time-effective method of fault detection and a means of identifying faults previously impossible with external test systems due to issues such as timing resolution. In coming years, there is some doubt that miniaturisation might be of a slower pace due to physical limitations in lithograph. It is believed that this will trigger the likelihood of front-end processes, testing and reliability development catching up technologically.
For more information contact Patrick Cairns, Frost & Sullivan, +27 (0)18 464 2402, [email protected], www.frost.com
© Technews Publishing (Pty) Ltd | All Rights Reserved
printer friendly version