IBM Research announced breakthrough results in developing a new family of experimental high-speed computer circuits that run at test speeds up to five times faster than today's top chips.
At the recent International Solid-State Circuits Conference in San Francisco, IBM showed an an innovative design for its new circuits. Called 'Interlocked Pipelined CMOS' the company said they reach speeds of 3,3 - 4,5 billion cycles/s (3,3 - 4,5 GHz) using conventional silicon transistors, and while dramatically reducing power consumption. The IBM researchers estimate that chips made with IPCMOS circuits would require only half the power used by a standard high-performance chip.
"To meet continuing demand for performance, we're going to have to look beyond simply making circuits smaller," said Dr Randall Isaac, Vice President, Systems, Technology, and Science, IBM Research. "Increasingly, performance gains will be driven by innovations in chip design. With breakthroughs such as our silicon-on-insulator technology moving into the market, and new circuit architectures and promising research like IPCMOS under way in our labs, IBM is building its arsenal for the era of multi-gigahertz chips."
Speeding up the clock
The key to the IPCMOS design is a distributed 'clock' function. In computer chips, the clock paces the speed of the circuits. Standard designs use a centralised clock to synchronise the operations of an entire chip, ensuring that all operations run at the same interval, or cycle. The clock waits for all the operations on a chip to finish before starting the next cycle, so the speed of the entire chip is limited to the pace of the slowest operation. To increase the speed, the IBM researchers decentralised the clock, using locally generated clocks to run smaller sections of circuits. IBM says this locally generated clock has two significant advantages:
* Speed - faster sections of circuits are free to run at higher cycles without needing to wait for slower operations to catch up.
* Power - the distributed IPCMOS clocks send signals locally only when an operation is being performed, significantly reducing power requirements. Centralised clocks send a signal to the entire chip, and the synchronising function can use as much as 2/3 of the total power consumed.
"Maintaining a synchronous clock across an entire chip becomes increasingly difficult as performance rises, and the clock itself can limit performance," said Stanley Schuster, one of the researchers working on IPCMOS. "We believe this new design will help us overcome those problems in future generations of high-speed chips."
Other IBM technology highlights presented at the conference were:
* 760 MHz S/390 G6 Microprocessor - a high-speed complex instruction set chip used in the first commercial server powered by copper interconnect technology, offering 27% frequency improvement over the previous-generation processor.
* 'Millipede' - a prototype micromechanical device for high-density storage that would use an array of 1000 tiny cantilevers to read and write data - with possible storage densities of over 400 billion bits per square inch.
* MRAM - an experimental solid-state memory technology that could someday lead to truly non-volatile random access memory with both the high speed of SRAM and the high density of DRAM.
Further information about IBM is available at www.ibm.com
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