Actel has announced that a new CompanionCore Alliance program partner, Eureka Technology, has optimised three PowerPC interface IP cores for use with its nonvolatile ProASICPLUS, Axcelerator, SX-A and RTSX-S field-programmable gate arrays (FPGAs).
With support for the PowerPC 603, 604, 740, 750 and 8260 bus protocols, the EP201 PowerPC Bus Master, EP100 PowerPC Bus Slave and EP300 PowerPC Bus Arbiter cores also support many advanced features of the PowerPC CPU bus architecture, including burst data transfers, data pipelining, extended data transfer sizes and support for multiple bus masters.
These IP cores are ideal for communications, military, aerospace, medical, industrial and automotive systems using or connecting to PowerPC microprocessors. The three PowerPC interface cores are available in VHDL and Verilog RTL source code formats and EDIF netlist formats.
For more information contact Kobus van Rooyen, ASIC Design Services, 011 315 8316, [email protected]
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