4i2i Communications has optimised its Viterbi and Reed-Solomon encoder and decoder intellectual property (IP) cores for use with Actel's nonvolatile, single-chip ProASICPLUS, Axcelerator, SX-A and RTSX-S field-programmable gate arrays (FPGAs). Furthermore, 4i2i has also optimised its JPEG encoders and decoders for Actel's high-performance Axcelerator device family.
Yankin Tanurhan, Applications and IP Solutions Group at Actel says, "4i2i's cost-effective DSP IP cores are a strong complement to Actel's nonvolatile flash- and antifuse-based FPGAs, enhancing designer productivity and reducing time to market for our mutual customers requiring forward error correction or multimedia functionality."
Consisting of a convolutional encoder and Viterbi decoder, the Viterbi IP core supports error correction for both burst mode and continuous data input. The core offers user-configurable parameters, including selectable code rates and interface widths, optional pseudo-BER calculation and in-phase detection. The Reed-Solomon encoder and decoder IP cores offer full-duplex encoding and decoding. The cores are also compatible with a variety of international telecommunication standards, including CCSDS, DECT, ADSL and xDSL. Offering full ISO 10918 standard compatibility, the JPEG encoder and decoder cores provide baseline JPEG compression capabilities, including up to 4080 x 4080 image resolution support and processing of up to 30 CIF frames per second.
For more information contact Kobus van Rooyen, ASIC Design Services, 011 315 8316, [email protected]
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