Hardware/software co-verification platform claimed to cut weeks off FPGA design time

Design Automation

8 October 2003 Design Automation

Aldec has announced that it has entered the embedded systems market with a new hardware/software co-verification platform. Called CoVer, the platform was developed for FPGA designs using soft-core microprocessors.

Aldec combined its proven HDL Design Entry and Verification software, Active-HDL, with the new CoVer technology, allowing both hardware and software teams to work in parallel on the same configuration of the design from day one. Complete debugging visibility is available to both teams at all times and throughout the entire design process, says Aldec.

Placing the processor and its related software into CoVer hardware, while putting all peripherals in Active-HDL, allows concurrent design verification by hardware and software teams. During data exchange between CoVer hardware and the Active-HDL simulator, the processor executes its program at between 100-200 kHz. When not communicating with the peripherals in Active-HDL, the processor runs in emulation mode at 16 MHz, says the company, while providing complete signal visibility and ultra fast debugging at any hierarchical level of the design.

CoVer provides direct event or transaction-based communication between the hardware and software design sections allowing reliable and efficient debugging and verification. It eliminates the need for cables, lab time, and 'stub code' and does away with having to continuously make new hardware prototypes for the software team.

The software team can start at the same time as the hardware team, and both teams can debug and test in parallel the same design configuration using tools that they are most comfortable with (editors, compilers, debuggers, simulators, etc). CoVer for the Xilinx MicroBlaze and Altera Nios processors are currently available.

For more information contact Franco Giangregorio, Parsec, 012 349 2282, [email protected]

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Hardware/software co-verification platform claimed to cut weeks off FPGA design time

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