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Xilinx' new FPGA architecture enables multiple domain-specific platforms
28 January 2004, Programmable Logic

Xilinx has announced what it calls a revolutionary new architecture that will enable rapid, cost-effective deployment of multiple domain-specific FPGA platforms with an optimal blend of features. The company's ASMBL architecture is a modular framework of silicon subsystems, enabling a new FPGA development methodology for rapid and cost-effective deployment of platforms targeted to different application domains. As a result, says Xilinx, customers will have a greater selection of devices, and will benefit from an up to 10x increase in capability for a given price point.

Xilinx plans to base future Xilinx Platform FPGAs on the new architecture. Built on more than 100 new technical innovations, the next generation Virtex Series Platform, slated for first half of 2004, will be the first FPGA family to use the new architecture. The new domain-specific devices will contain more than 1 billion transistors in a single device.

The highly modular ASMBL architecture makes use of advanced flip-chip packaging technology and eliminates geometric layout constraints associated with traditional chip design such as hard dependencies between I/O count and fabric array size. ASMBL also addresses the increasingly more stringent requirements for on-chip power and ground distribution by allowing power and ground to be placed anywhere on the chip. As a result, Xilinx can significantly accelerate the development time and increase reliability when developing platform FPGAs.

"Moore's Law as well as advances in packaging technologies continue to propel programmable logic to new heights of capacity and performance," said Wim Roelandts, chief executive officer at Xilinx. "The ASMBL architecture will allow Xilinx to further penetrate the $23 billion dollar ASIC and ASSP markets with aggressive cost points never before possible."

As FPGAs continue to assume more and more of the ASIC and ASSP markets, Xilinx FPGAs are being proliferated into many new types of applications. The ASMBL architecture will allow Xilinx to quickly react to changing customer needs. With the delivery of the next-generation Virtex Series, Xilinx says that customers will be able to choose the right platform most suitable for their application, with the optimal mix of logic, memory, serial I/O, parallel I/O, embedded processors, DSP, clock management, hard IP, mixed signal, and other functionality.

For more information contact Avnet Kopp, 011 809 6100, or Memec SA, 011 897 8600.


Credit(s)
Supplied By: Avnet South Africa
Tel: +27 11 319 8600
Fax: +27 11 319 8650
Email: sales@avnet.co.za
www: www.avnet.co.za
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