VHDL software has improved performance and functionality
24 March 2004
Design Automation
Aldec's Active-HDL 6.2, in addition to a two-times performance increase over the previous version, now includes an improved Advanced Dataflow, Library Encryption, Branch Coverage and X-Trace, according to the manufacturer. The advancements provide industry-leading performance not only in verification times, but its new features simplify the design creation and debugging process for VHDL, Verilog and mixed language designs.
The behavioural, gate-level and timing simulation performance has been improved, while the Advanced Dataflow window allows the designer to explore the connectivity of the simulated design and analyse the dataflow among instances, concurrent statements, signals, nets and registers. Design objects are displayed in the diagram window and can be viewed in hierarchical or flattened modes.
Branch coverage has been added to Active-HDL 6.2 and gives the user additional assurance that the HDL code is correctly tested by the testbench. In addition to line, unit and toggle coverage, this makes the code coverage program an invaluable tool for high reliability designs.
The X-Trace command creates a report with information about unknown values in the simulation model. Each X-Trace report entry can be saved as a text or HTML file and includes simulation time and full hierarchical names of the signal that experienced an unknown value.
Further improvements are that Active HDL 6.2 now supports encrypted libraries for protecting HDL code compiled in the design. A workspace Splitter that allows up to four windows in one integrated desktop frame, Pre-compiled SystemC libraries, Matlab/Simulink, Celoxica interface and Asian Language support are also part of the new release.
For more information contact Franco Giangregorio, Parsec, 012 349 2282, [email protected]
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