RTL debugging software for PFGAs enhanced
21 April 2004
Design Automation
Access Control & Identity Management
Products & Solutions
Synplicity has enhanced its Identify RTL debugging software to further accelerate FPGA hardware debugging. The Identify 1.3 software features a new source code encapsulation and encryption feature that provides designers with better access to source code and makes source code more secure. This latest version features support of additional devices from Altera and Xilinx. It also features multiple debugger synchronisation, enabling multiple debuggers to run on a single PC while accessing the same hardware. Other features within the software include Verilog 2001 support and black box attribute support.
The Identify RTL debugging software has been enhanced with the addition of a new source code encapsulation and encryption feature. This new ability to encapsulate or package the RTL source for debugging allows designers to easily transfer projects to PCs in a lab without network access. The new software version also uses Blowfish encryption technology to optionally allow the RTL source code to be encrypted, allowing designers to debug hardware even in unsecure environments.
This version of the Identify software also features multiple debugger synchronisation, allowing multiple debuggers to be run on the same PC, talking to the same hardware board via a single JTAG connection and waiting for triggers to happen. This feature is especially useful on boards with multiple devices where designers want to test for multiple asynchronous conditions.
In addition to the software's new support for Altera's Cyclone and Xilinx's Spartan-3 FPGAs, additional devices supported by the Identify 1.3 software include Altera Apex, Apex-II and Stratix FPGAs; Actel ProASIC and ProASIC Plus FPGAs; and Xilinx Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II and Virtex-II Pro FPGAs.
For more information contact Franco Giangregorio, Parsec, 012 349 2282, franco@parsec.co.za
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