Update on Intel's latest 65 nm achievement
22 September 2004
News
Intel has built fully functional 70-megabit static random access memory (SRAM) chips with more than half a billion transistors using 65 nanometer (nm) process technology. The transistors have transistor gates measuring 35 nm, approximately 30% smaller than the gate lengths on the previous 90 nm technology. Intel says its new 65 nm process also includes several unique power-saving and performance-enhancing features.
Intel's strained silicon technology, first implemented in its 90 nm process, is further enhanced in the 65 nm technology. In this second generation, transistor performance is increased by 10 to 15% without increasing leakage, it says. The 65 nm transistors have a reduced gate length of 35 nm and a gate oxide thickness of 1,2 nm, which combine to provide improved performance and reduced gate capacitance. Reduced gate capacitance ultimately lowers a chip's active power.
The new process also integrates eight copper interconnect layers and uses a 'low-k' dielectric material that increases signal speed and reduces chip power consumption. Intel has also implemented 'sleep transistors' that shut off the current flow to large blocks of the SRAM when they are not being used, which eliminates a significant source of power drain.
www.intel.com/research/silicon
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