Electronics Technology


Faster mixed VHDL and Verilog design

17 November 2004 Electronics Technology Information Security News & Events

Aldec increased the performance of its Riviera 2004.04 over the previous release, yielding as much as a 2x speed-up for mixed VHDL and Verilog designs. The performance increase was achieved by optimising the communication between language compilers and additional optimisation of the VHDL and Verilog compilers individually. Additional performance increases were achieved with the new waveform database structure in Riviera 2004.04. It now includes new debugging and graphical interface improvements to provide customers with one of the fastest operating system-independent RTL debugging environments available.



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