Building on nearly 15 years of CPLD leadership and innovation, Altera released its MAX II family last year. The MAX II devices are based on a new look-up table (LUT)-based architecture that it claims delivers the lowest cost per I/O pin on the market and breaks new ground in CPLD architectures. This instant-on, non-volatile device family targets general-purpose, low density logic applications, enabling designers to leverage the benefits of industry leading CPLD devices in lieu of small ASICs and ASSPs, which are costlier and less flexible.
These MAX II devices operate at approximately one-tenth the power of the previous-generation of MAX devices. They offer densities ranging from 240 to 2210 logic elements (LEs) (192 to 1700 equivalent macrocells) and up to 272 user I/O pins.
MAX II devices include many new features. The device family was specifically designed to reduce costs for both new and traditional CPLD applications. Notable features include:
* One-tenth the power consumption of prior CPLD families.
* Quadruple the density - The density range in macrocell equivalents is approximately 192 to 1700 macrocells. This quadruples what Altera offered in previous families.
* Twice the performance - The MAX II device family performance is on average 2X faster than the MAX 7000AE family as a result of improvements in routing architecture, software algorithms, and process technology.
* User flash memory - Altera is the first programmable logic supplier to offer user flash memory embedded within a programmable logic device (PLD). The MAX II device family can therefore integrate commonly used serial or parallel EEPROMs. The memory capacity per device is 8 Kbits across the entire family.
* Realtime in-system programmability (ISP) - devices can be configured in realtime without interrupting functionality.
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