Underscoring its efforts to simplify the design of embedded systems, Actel has unveiled an expanded design infrastructure in support of its single-chip M7AFS device: the ARM7-enabled version of the company's mixed-signal Actel Fusion programmable system chip (PSC). Contents of the new infrastructure include the CoreAI (Analog Interface) IP core, and optimised versions of Actel's CoreConsole IP Deployment Platform (IDP) and Libero Integrated Design Environment (IDE).
With this enhanced development environment, Actel says that designers are offered the capability to quickly and easily implement the industry's only ARM7-enabled, mixed-signal FPGA for real-world applications ranging from communications to automotive, industrial and consumer.
Notes Jake Chuang, a senior marketing director at Actel, "The combination of Actel's single-chip ARM7-enabled Fusion PSCs, the CoreMP7 soft ARM7 processor and this comprehensive design infrastructure frees designers from the need to settle for multichip solutions to complete their mixed-signal designs. Additionally, the free availability of CoreAI, the optimised CoreConsole 1.1 IDP and Actel Libero IDE, significantly reduces the risk and costs associated with the development of feature-rich embedded systems."
Tool optimisations ease embedded design
CoreAI IP block allows the CoreMP7 soft ARM7 processor core to interface with the analog resources on Actel's M7 Fusion devices through the Advanced Peripheral Bus (APB), enabling designers to directly control and configure the analog peripherals. It offers ADC conversion controlled by CoreMP7 and an APB slave interface with 8- or 16-bit width and 14 maskable interrupt sources. Also, an internal clock divider in CoreAI generates an Analog Configuration Mux clock, and an optional-read FIFO stores up to 256 ADC conversions.
Simplifying the assembly of IP cores within M7AFS designs, the free CoreConsole 1.1 IDP allows users to focus on the system rather than individual components, says Actel, resulting in significant reductions of time and cost in overall development. In addition, CoreConsole 1.1 provides access to CoreAI through an integrated 'IP Vault' as well as to Actel's entire DirectCore IP library, full AHB multimaster support, software driver export and memory map generation, and free CoreMP7 subsystem IP block updates.
Also available for free, Libero 7.1 IDE Gold allows users to instantly begin implementing ARM7-enabled, mixed-signal FPGA designs up to one million system gates. Optimisations to Libero 7.1 include design support for the first device in the M7AFS family, the M7AFS600. Additionally, the SmartGen core generator tool within the Libero IDE enables the configuration of the analog capabilities of M7AFS devices accessible through CoreAI.
Actel's Core AI is available for free. Also free, the CoreConsole 1.1 IDP and Libero 7.1 IDE Gold is available for download via Actel's website.
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