MCU combines SRAM, flash and Ethernet

DSP, Micros & Memory

31 May 2006 DSP, Micros & Memory

STMicroelectronics' new 32-bit microcontroller family, the STR910F devices, employ an ARM966E-STM core that it claims brings substantial benefits compared to ARM7TDMI cores. The STR910F series was specifically developed to meet the growing demand for higher-performance embedded-control applications and to enable Ethernet connectivity. The ARM966E-STM CPU core accesses its instruction and data memories using two separate internal busses, enabling simultaneous access of both code and data. Each of these memories is attached to the core through a highly optimised tightly-coupled memory (TCM) interface for rapid access. The STR910F exploits this architecture by placing a high-speed burst Flash memory on the Instruction TCM, and a zero-latency SRAM on the Data TCM. The result is 96 MIPS peak code execution at 96 MHz (claimed to be the highest peak performance for general-purpose Flash ARM-based MCUs), and extremely efficient data movement between the CPU core and SRAM. In contrast, the ARM7TDMI CPU core shares a single bus for access to its instruction and data memories, making simultaneous access impossible. Additionally, the ARM966E-STM core supports single-cycle DSP instructions, satisfying both control and signal-processing requirements.

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DSP, Micros & Memory

MCU combines SRAM, flash and Ethernet

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