Arithmatica's CellMath tools now include Verilog interface
28 June 2006
Design Automation
Verific Design Automation has licensed its hardware description language (HDL) component software to Arithmatica, the first company focused solely on using advances in silicon math algorithms to lower costs and power and increase speed for maths-intensive ICs. Such ICs are used in 3D graphics, imaging, multimedia, wireline and wireless communications, and embedded processing.
Verific Design Automation develops and sells C++ source code-based SystemVerilog, Verilog and VHDL front ends - parsers, analysers and elaborators - as well as a generic hierarchical netlist database for EDA applications.
Arithmatica says it integrated Verific's Verilog parser and register transfer level (RTL) elaborator with its CellMath tools to provide tighter flow integration for Verilog users. The newly-released CellMath Verilog interface feature provides Verilog designers familiar and easy-to-use syntax to specify robust datapath structures. The Verilog input language uses pragmas to explicitly instantiate advanced arithmetic datatypes such as carrysave wires and features such as internal rounding.
Additionally, the companies have worked jointly on partitioning datapath logic within a logic module for synthesis in CellMath Designer, further streamlining the Verilog hardware designer's implementation flow.
For more information see www.arithmatica.com and www.verific.com
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