STMicroelectronics became the first company to combine Ethernet connectivity, an ARM9E processor core, and large embedded SRAM and Flash memories in a general-purpose Flash microcontroller family with its STR910F series.
This ARM-based Flash MCU creates many new possibilities for system designers to transform powerful embedded-control applications into low-cost LAN or Internet nodes. The STR910F series was specifically developed to meet the growing demand for higher-performance embedded-control applications and to enable Ethernet connectivity. An extension to ST's successful STR7XX series of ARM7TDMI-based MCUs, applications such as PoS terminals and peripherals, vending machines, industrial control and factory automation, serial-protocol gateways, building automation, security and surveillance applications, and portable instrumentation are increasingly demanding higher performance and network connectivity. In addition, they are also requiring larger embedded program/data flash and especially SRAM memories.
The STR910F devices employ an ARM966E-S core, which accesses its instruction and data memories using two separate internal busses, enabling simultaneous access of both code and data. Each of these memories is attached to the core through a highly optimised interface for rapid access. The STR910F exploits this architecture by placing a high-speed burst Flash memory on the Instruction TCM, and a zero-latency SRAM on the Data TCM. The result is 96 MIPS peak code execution at 96 MHz, and extremely efficient data movement between the CPU core and SRAM.
The ARM966E-S core also supports single-cycle DSP instructions, enabling the STR910F to satisfy both control and signal-processing requirements. This gives clear advantages over traditional solutions based on separate DSP and control processors.
Traditionally, ARM9E cores are used to build ROMless microprocessors that have a complex memory management unit (MMU) operating with internal cache and external synchronous RAM, all loaded at boot-up from an external Flash memory. Instead of an MMU with cache, the STR910F supports a simple memory model well suited for compact realtime operating systems (RTOS). It also uses an innovative memory accelerator to boost performance during non-sequential code execution from burst Flash memory, giving better realtime control behaviour than traditional cache memory.
The STR910F was given large memories to support the use of RTOS and TCP/IP stacks, in addition to complex control applications. SRAM sizes range up to 96 KB. Uniquely, this SRAM can be protected by a battery or super-capacitor, and optionally the SRAM contents can be automatically destroyed for secure applications in response to a signal on the tamper-detection input pin. Flash memory sizes range up to 544 KB. Each of the SRAM and Flash memories may be used for either instructions or data.
There are many high-speed communication channels on the STR910F, and up to nine full-featured direct memory access (DMA) channels to support them. These DMA controllers effectively allow peripherals on the advanced high-performance bus (AHB) and advanced peripheral bus (APB) to act as a master to the SRAM, sharing SRAM access with the CPU through a specially-designed arbitrator for extremely streamlined data flow. For example, the Ethernet DMA controller can support the movement of 91 Mbps of raw Ethernet frames between the MAC and the SRAM, with only 10% CPU loading.
STR910F MCU series support a full set of peripherals in addition to the Ethernet MAC. They include USB Full Speed, CAN, three UART/IrDA, two SPI, two I²C, eight channel 10-bit ADC, four 16-bit timers, a 3-phase AC motor control unit, complete supervisor functions with low voltage reset and brown-out detect, a full-featured realtime clock, an external memory interface, an ETM9 debug and trace interface, and up to 80 5 V tolerant I/O.
The embedded realtime clock has features typically found only on external RTC devices. It has full calendar and alarm functions, and will also time-stamp an event on the Tamper input pin.
The STR910F family also encompasses comprehensive power conservation and supervisor features. Power consumption can be dynamically adjusted, giving the CPU the ability to gate and scale the system and peripheral clocks at any time to balance performance demand and power consumption.
Comprehensive support is offered from ST and third parties, with starter kits from Hitex, IAR, Keil, and Raisonance. Kits include compiler and debugger (limited code size), a JTAG debugging and programming cable, code examples, and all necessary hardware to begin a design. ST provides an evaluation board for hardware evaluation of all interfaces and I/O of the STR910F. Demonstration code is available free of charge from ST.
Six part numbers are offered, packaged as LQFP80 and LQFP128, with the LQFP128 packages. SRAM ranges from 64 KB to 96 KB and Flash memory ranges from 288 K to 544 KB. The core operates at 1,8 V ±10%, and the I/O ring at 2,7-3,6 V over temperatures of -40 to 85°C.
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