At the Embedded Systems Conference in April in San Jose, Atmel launched what it claims is the industry’s lowest power 32-bit Flash microcontrollers with DSP instructions.
Based on Atmel's AVR32 UC core, also announced the same day, the UC3A Series microcontrollers deliver 80 Dhrystone MIPS and consume only 40 mA at 66 MHz when operating from a 3,3 V power supply. Atmel said that this is significantly lower than some of the closest industry competitors.
The AVR32 UC3 core is the second core to be based on Atmel's AVR32 architecture, launched last year. It has single cycle DSP instructions that include multipliers and multiply-and-accumulate, and executes 1,3 Dhrystone MIPS/MHz.
Single-cycle instructions
The AVR32 UC core, system bus matrix, memory subsystem and peripherals were designed from the ground up, as a whole, to ensure optimum performance. And it was designed specifically to interface to on-chip Flash memories. The Flash on UC3A Series devices uses a pipelined, dual-bank architecture that outputs one word every clock cycle when executing sequential code, with or without a wait state. Employing a wait-state allows microcontrollers' clock frequency to be increased from 40 MHz to 66 MHz, and results in a negligible reduction in per cycle throughput of only 8% - from 1,3 to 1,2 Dhrystone MIPS/MHz.
Dynamic frequency scaling
The UC3A Series MCUs have a six-layer high speed bus matrix with point-to-point connections from all masters to all slaves, enabling masters to concurrently access any slave at a maximum speed of 264 MBps at 66 MHz. If multiple masters wish to access the same slave, arbitration is automatically performed. The bus masters are the AVR32 UC core data and instruction interfaces, peripheral DMA controller, and several high speed peripherals. The bus slaves are the on-chip SRAM and Flash memories, USB, the two peripheral bus bridges, and the external bus interface (EBI).
The 15 channel peripheral DMA controller on the UC3A Series connects each peripheral directly to the entire addressable memory system, enabling high bandwidth data transfers without any processor overhead. Conventional processors, which require the CPU to transfer data one byte at a time, consume 55% of their processing resources at just 250 KBps and 100% of it at 500 KBps. The peripheral DMA on UC3A Series MCUs provides 15 DMA channels with a total available bandwidth of 24 MBps.
10/100-Mbps Ethernet
Configurable in full- or half-duplex modes, the UC3A Series' Ethernet MAC has dedicated DMA, a programmable interpacket gap, support for virtual-LAN tagged frames and automatic-pause frame generation and termination. A dual mode interface offers a seamless media independent interface (MII) with a large selection of PHYs for Fast Ethernet applications, or a reduced media independent interface (RMII) which uses less I/O.
A full speed (12 Mbps) USB 2.0 device with on-the-go (OTG) capability has dedicated DMA, can interface to a personal computer as a device, and can behave as a USB host to support small USB devices such as USB Flash keys, printers, keyboards or mice.
Communications interfaces include two master/slave serial parallel interfaces (SPIs), one synchronous serial controller (SSC), one master/slave two-wire interface (TWI) and four USARTs with hardware flow-control. One USART has special extensions to support modem, IrDA and smartcard ISO7816 serial protocols.
UC3A Series microcontrollers are available with an external bus interface (EBI) that extends the addressable physical memory to 16 MB. Its non-multiplexed 16-bit data bus can interface to high density external SRAM, SDRAM, ROM, Flash devices and memory-mapped devices such as LCDs or FPGAs.
Devices have three 16-bit timers and seven pulse width modulators (PWM) that can trigger the 10-bit 8-channel ADC to ease electrical motor control design.
The on-chip system manager includes an internal voltage regulator for 3,3 V single power supply operation, power-on reset, brown-out detector, hardware watchdog timer and a realtime timer. The clock system provides an on-chip RC oscillator, two high frequency external oscillators, one 32 kHz oscillator and two independent on-chip PLLs. Special security options are available to protect Flash content from being corrupted by the application itself or from being read from external unauthorised access.
The active mode the compact nature of the instruction set and the tight coupling of the memories to the processor minimises the number of power-consuming memory accesses. In addition, two separate peripheral bus bridges allow different clock frequencies to be set for high- and low-speed peripherals, so slower peripherals can operate on a slower bus that draws less power. The frequencies of the two bus bridges and the CPU clock can be individually and dynamically configured to the lowest possible frequency that allows the system to operate. Individual clocks can also be completely switched off.
Any section of the UC3A device that is not in use can be switched off by disabling its clock. The UC3 core uses a multithreshold transistor library to reduce static power consumption. UC3A Series standby power consumption is just 40 μA, and operating power consumption is 40 mA at 66 MHz with all clocks active (600 μA/MHz).
For more information contact Thomas Page, Atmel, +27 (0)12 349 2262, [email protected]
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