Programmable Logic


Robust simulation models provide comprehensive timing data for FPGA-prototyped ASIC designs

14 February 2001 Programmable Logic

Clear Logic now offers a comprehensive web-based capability to provide simulation models for its CL10K family of link-configured ASICs. Designers of Clear Logic ASICs use programmable FPGAs from Altera for prototyping, dramatically reducing ASIC development costs and time-to-market, claims Clear Logic. The company says it migrates the bitstream from the prototype FPGA directly to the company's ASIC without any modification, redesign or 'conversion'. Clear Logic does the migration at its factory, and the resulting ASICs operate identically to the FPGA prototype in the same socket. The simulation models provide much more complete timing and hierarchy information than those provided by the tools from the FPGA manufacturer, it says.

According to Don Knowlton, Clear Logic's Vice President of Marketing, "ASIC designers expect to simulate their designs very thoroughly to ensure functionality and timing. Since Altera FPGAs are used to prototype Clear Logic ASICs, designers have been forced to rely on FPGA simulation models generated by Altera's FPGA design tools. However, we were appalled by the lack of complete timing information in these models. They provide only worst cases for propagation delay, and set-up and hold timing. If variations in operating temperature, power supply voltage, or the silicon manufacturing process cause the device to operate with shorter delays than the worst cases, the design could fail in an actual operating environment, even though it simulated successfully using the FPGA models. For example, a pulse that appears wide enough in the simulation done using the models from the FPGA vendor may be too short when the system operating environment varies. In the case of a pulse generated to control writing to a memory, the data stored in the memory would be corrupted, potentially causing catastrophic system failure.

"Another weakness of the Altera models is that they remove most of the design hierarchy, presenting an essentially flat model of AND, OR, NAND and XOR gates that is virtually impossible to trace back to the original schematic or to the physical implementation in the FPGA's coarse-grained logic elements. As a result there is really no practical way for a designer to trace the actual signal routing to determine what options are available to correct a timing error uncovered in the simulation.

"In order to give our customers maximum control over their designs, Clear Logic has developed its own simulation models for Clear Logic ASICs. Our models are based on the customers' bitstream. However, Clear Logic's simulation models preserve the design's hierarchy and also provide comprehensive information on minimum, typical and maximum delays for each internal circuit. These models give designers the power to accurately simulate their design and to explore alternatives that can radically improve performance or design margins," Knowlton added.

Clear Logic gives the following key advantages:

* Allows identification of problems associated with short pulse widths.

* Allows designers to evaluate other options.

* Helps the designer locate the source of the problem on the device layout.

* Models work with all third-party Verilog simulation tools.

* Verilog models delivered within 24 h over the Internet.

Since Clear Logic generates the models for the customer, it says there is no need to purchase any additional EDA tools or to purchase software upgrades to support newer devices, as is the case when using models from FPGA vendors. Clear Logic also does not charge for the models. VHDL models for Clear Logic designs will be available during 2001.



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