Telecoms, Datacoms, Wireless, IoT


Telecom timing IC enables up to 10 G synchronous Ethernet

19 September 2007 Telecoms, Datacoms, Wireless, IoT

Maxim recently introduced the DS3104 IC to provide full carrier-class clock synchronisation for new synchronous Ethernet (SyncE) line cards and mixed SONET/SDH/SyncE line cards.

Key DS3104 innovations include two independent DPLLs for bidirectional frequency conversion between Ethernet clock rates and SONET/SDH rates, and complete support for all 1 G, 10 G, and 100 M Ethernet MII clock rates. Applications include line cards and other subsystems in a wide variety of wireline and wireless systems, including ADMs, digital cross-connects, carrier-class switches and routers, wireless base-stations, DSLAMs and multiservice access nodes.

The DS3104 has eight available clock inputs, and each can be assigned to either of the two internal DPLLs. Inputs are continually monitored for quality and can be automatically qualified and disqualified by the device according to configurable criteria. Four clock inputs are CMOS/TTL, the other four are LVDS/LVPECL or CMOS/TTL. The eight clock inputs accept all common telecom clock rates.

The DPLLs in the DS3104 can direct-lock to a number of common telecom frequencies. The DPLLs can also lock to integer multiples of the direct-lock frequencies by using programmable input dividers. DPLL bandwidths are programmable from 1 Hz to 600 Hz, and a variety of damping factors are available. The main DPLL can optionally use phase build-out techniques to perform hitless switching to the secondary system clock when the primary system clock fails. Typical output-clock phase movement in this scenario is less than one nanosecond, even when the device is clocked by an inexpensive crystal oscillator that is not temperature-compensated. The main DPLL also has a precise digital holdover mode to maintain output clocks in case both system clock references fail or are unavailable.

The DS3104 can produce a total of seven output-clock frequencies simultaneously, plus 2 kHz and 8 kHz frame pulses. Each output clock can be frequency-locked to either of the two DPLLs for maximum flexibility. For combination SONET/SDH/SyncE line cards, the device can simultaneously produce SONET/SDH rates (eg, 155,52 MHz), the 1 G Ethernet GMII clock rate (125 MHz), and the 10 G Ethernet XGMII clock rate (156,25 MHz or 312,5 MHz). All rates are frequency-locked to the selected system clock through the main DPLL. Of the seven output clocks, three are CMOS/TTL, two are LVDS/LVPECL, and two are dual CMOS/TTL and LVDS/LVPECL.

The device has an SPI serial bus interface and is packaged in an 81-lead, 10 mm x 10 mm BGA and operates over the full industrial temperature range of -40°C to +85°C.



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