Altera has announced that it has achieved DDR3 memory interface speeds in excess of 1067 Mbps with its Stratix III FPGAs, providing a claimed 33% advantage in memory performance over competing FPGA solutions. This higher memory bandwidth enables new communications, computing and video processing applications that were either previously impossible or required doubling the number of memory banks.
Designed to address the benefits of DDR3 memory, Altera's Stratix III family includes read and write levelling, I/O delay for DQ de-skew, dynamic on-chip termination, and the use of a reconfigurable phase-locked loop (PLL) to compensate for voltage and temperature variations.
In addition, Altera's Quartus II software version 7.2 includes a DDR3 PHY wizard and controller intellectual property (IP), which substantially simplifies high-performance memory interface design by automatically adapting to DIMMs from a variety of memory suppliers.
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