Lattice Semiconductor has today announced its new, low power complex programmable logic devices (CPLD), the 1,8 V ispMACH 4000ZE family.
This second-generation in-system programmable CPLD family is ideally suited to low power, high volume portable applications, with typical standby current as low as 10 μA.
The feature rich ispMACH 4000ZE devices offer ultra-small, space saving chip scale ball grid array (csBGA) package options, a new Power Guard feature that provides ultra-low system power, and new system integration capabilities, including an on-chip user oscillator and timer. The family is offered in four logic densities, from 32 to 256 macrocells.
The ispMACH 4000ZE family offers enhanced system features such as per pin pull-up, pull-down or bus keeper control; an on-chip user oscillator and timer; and input hysteresis. The Power Guard feature lowers power consumption by selectively disabling unused input pins so that their switching does not consume dynamic power needlessly. This feature consists of an enabling multiplexer between the I/O pin and the input buffer and its associated circuitry inside the device. All I/O pins in a block share a common block input enable (BIE) signal. Depending on the device size, there can be from two to 16 blocks per device. Any I/O pin in the block can be programmed to ignore the BIE signal, allowing the Power Guard feature to be enabled or disabled on a pin-by-pin basis.
An internal oscillator is also provided for use in miscellaneous housekeeping functions such as watchdog 'heartbeat', digital de-glitch circuits and control state machines. The 4000ZE family also offers 'always on' input hysteresis for each pin. This new feature provides improved noise immunity for 3,3 V and 2,5 V inputs.
The ispMACH 4000ZE devices operate from a nominal 1,8 V power supply with operation extended down to 1,6 V, accommodating extended end-of-battery-life voltages that can provide useful added margin for many systems. They have two I/O banks, each with its own power supply voltage that can be set at the appropriate level to support LVTTL and LVCMOS 3,3, 2,5, 1,8 and 1,5 V outputs. The device input buffers have programmable thresholds that support the above standards independent of the I/O bank voltage. The I/Os are 5 V tolerant to facilitate connection to legacy chips and interfaces. All devices are Boundary Scan Testable and in-system programmable through an IEEE 1532-compliant JTAG boundary scan (IEEE 1149.1) interface.
The ispMACH 4000ZE family is supported by Lattice's ispLEVER Classic design tool suite, which includes a powerful suite of tools supporting all design tasks, including project management, HDL design entry, module/IP integration, place and route, timing analysis and programming.
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