Exar has added a T1/E1/J1 framer and LIU combination with next generation capabilities and features to its portfolio of T/E solutions.
The single-channel XRT86VL30 targets telecommunications equipment including wireless base-stations, digital access and cross connect systems, channel service units (CSUs) and voice over packet gateways.
The device is a single-channel physical-layer processor incorporating a T1/E1 (1,544 or 2,048 Mbps) framer and an LIU. Each framer has both a framing synchroniser and transmit and receive slip buffers. Each framer also contains transmit and overhead data input ports, which permits data line terminal equipment direct access to the outbound T1/E1/J1 frames. In the receive direction, it has complementary blocks to the transmit path and in addition, includes a PRBS, QRSS and network loop up/down code generator/detector. The device detects standard framing and signal error conditions. The flexible microprocessor interface allows for easy configuration, control and status monitoring.
The XRT86VL30’s line interface portion offers uninterrupted data transmission which is critical for applications including clock and data recovery circuitry, T1 compliant line build out, and a crystal-less jitter attenuator for each channel. All of these are necessary for successfully transmitting and receiving T1, E1 and J1 signals.
The device supports Exar’s R³ technology, making it reconfigurable with integrated termination supporting all common T1/E1/J1 line impedances, enabling customers to build a simple board and eliminate the need for external relays for 1:1 and 1+1 redundancy applications. This feature allows final device configuration to be made just prior to line-card installation. This capability prevents customers from having to unnecessarily stockpile an inventory of all configurations to accommodate changing market conditions.
The XRT86VL30 fully meets all of the latest T1/E1/J1 specifications and its extensive test and diagnostic functions include loop-backs, boundary scan, pseudo random bit sequence (PRBS) test pattern generation, performance monitor, bit error rate (BER) meter, forced error insertion, and LAPD unchannelised data payload processing according to ITU-T standard Q.921.
| Tel: | +27 11 315 8316 |
| Email: | [email protected] |
| www: | www.asic.co.za |
| Articles: | More information and articles about ASIC Design Services |
© Technews Publishing (Pty) Ltd | All Rights Reserved
printer friendly version