New from National Semiconductor is a family of clock jitter cleaners capable of providing ultra low-noise clocks without external high-performance voltage-controlled crystal oscillator (VCXO) modules.
Using a simple external crystal and cascaded PLLatinum architecture, the devices provide sub-200 femtosecond RMS jitter to improve system performance and accuracy.
The new LMK04000 family consists of five precision clock conditioners: LMK04000B, LMK04001B, LMK04011B, LMK04031B and LMK04033B. These devices feature power-to-noise specifications that place them among National’s PowerWise family of energy-efficient products. The LMK04000B and LMK04001B offer 24,4 mW-ps per channel, while the LMK04031B and LMK04033B are rated at 25,4 mW-ps per channel and the LMK04011B at 37,4 mW-ps per channel.
The devices provide clean clocks to analog-to-digital converters (ADC), digital-to-analog converters (DAC) and other high-performance components used in wireless infrastructure, test and measurement, and medical ultrasound and imaging equipment. Wireless base station applications include single-carrier and multicarrier GSM, long term evolution (LTE), universal mobile telecommunications system (UMTS), worldwide interoperability for microwave access (WiMAX) and Code Division Multiple Access (CDMA) networks.
The new LMK04000 family uses National’s cascaded PLLatinum architecture, which consists of two high-performance cascaded phase-locked loops (PLL), a low-noise crystal oscillator circuit, a high-performance integrated VCO as well as low-noise dividers and drivers. The first PLL can be configured to use a simple external crystal or a VCXO module to provide the jitter cleaning function while the second PLL uses the integrated VCO to perform low-noise clock generation.
These devices feature dual redundant inputs, five differential outputs and an optional default clock upon power-up. The input block is equipped with loss-of-signal detection and automatic or manual selection of the reference clock. Each clock output pair consists of a programmable divider, a phase synchronisation circuit, a programmable delay and either a low-voltage differential signalling (LVDS), low-voltage positive-emitter-coupled logic (LVPECL) or low-voltage CMOS (LVCMOS) output driver. The LVPECL and LVDS outputs support clock rates up to 1080 MHz, while the LVCMOS outputs reach up to 250 MHz. The default clock can be used to provide an initial clock for the field-programmable gate array (FPGA) or the microcontroller that programs the clock jitter cleaner during the system power-up sequence.
For more information contact EBV Electrolink, +27 (0)21 402 1940, [email protected], www.ebv.com
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