Altera has unveiled Quartus II software version 8.1, which aims to speed development times by automating traditionally time-consuming features.
The design partition planner, introduced in the previous version of Quartus II, now provides automated partitioning in version 8.1, allowing more designers to leverage the productivity benefits of incremental compilation. Quartus II now also eliminates the need to modify gated clocks manually by automatically converting gated clocks to functionally equivalent logic supported by the FPGA architecture. Automating these features allows design teams to focus more effort on value-added portions of the design.
Version 8.1 adds Stratix IV pin-outs and support for a new Stratix IV FPGA speed grade offered in a low-cost package. The software provides added transceiver timing-model support, as well as support for 8,5 Gbps transceivers, 1,6 Gbps LVDS and 400 MHz DDR memory. For designers targeting a HardCopy ASIC implementation, Quartus II software provides initial support for HardCopy IV ASICs.
New features in version 8.1 include an embedded logic analyser, new HDL templates for the SOPC Builder tool, a new Avalon memory-mapped half-rate bridge and support for Red Hat Enterprise Linux 5 and CentOS 4/5 (32 bit/64 bit) operating systems. The new release also boasts an enhanced third-party simulation interface, a new pin-out advisor, Real Intent verification support, as well as new and enhanced IP cores and megafunctions.
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