Altera has announced two new FPGA families with integrated transceivers. The new Stratix IV GT and Arria II GX 40 nm FPGA families join Stratix IV GX FPGAs and HardCopy IV GX ASICs to expand the company’s broad portfolio of transceiver FPGA and ASIC solutions.
This portfolio offers transceiver speeds from 155 Mbps to 11,3 Gbps to address a wide range of applications, from cost sensitive video cameras to ultra-high-performance backhaul systems.
The Arria II GX, Stratix IV GT, and Stratix IV GX FPGAs and HardCopy IV GX ASICs utilise common transceiver technology and are supported by a common set of development tools that enable system designers to develop full system-on-chip (SoC) solutions. This portfolio delivers both FPGA solutions from 16 000 logic elements (LEs) to 530 000 LEs, and HardCopy ASIC solutions of up to 11,5 million ASIC gates.
The highest performing of the new FPGAs, Stratix IV GT devices – with integrated transceivers operating at 11,3 Gbps – are optimised specifically for 40G and 100G applications such as communications systems, high-end test equipment and military communications systems. They have 24 transceivers operating at 11,3 Gbps, and an additional 24 transceivers operating at 6,5 Gbps, to deliver a very high bandwidth solution. The FPGAs also offer up to 530 000 LEs, 20,3 Mb internal RAM and 1288 18 x 18 multipliers.
Arria II GX devices are low-power 3,75 Gbps transceiver FPGAs and are cost optimised for applications using mainstream protocols such as PCI Express (PCIe) and Gigabit Ethernet (GbE). They feature up to sixteen 3,75 Gbps transceivers, 256 000 LEs and 8,5 Mb of internal RAM. In addition, they support targeted protocols such as CPRI for LTE and WiMAX wireless infrastructure access equipment, GPON and XAUI for wireline infrastructure access and networking equipment, and triple-speed SDI for broadcast and other video processing equipment. A collection of reference designs and design examples is available to accelerate development.
The FPGAs and HardCopy ASICs in Altera’s transceiver portfolio are supported by Altera’s new Quartus II design software version 9.0. The design software provides a single tool suite for all FPGA and ASIC products, complemented by one IP set and a common transceiver technology. Altera also provides a suite of tools to ease transceiver integration and board design, including the Pre-Emphasis and Link Estimation (PELE) tool, the power distribution network (PDN) tool, and the Early Simultaneous Switching Noise (SSN) Estimator, as well as SPICE and IBIS simulation models and a board design guideline document.
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