6- and 12-channel clock fanout buffers

22 July 2009 Analogue, Mixed Signal, LSI

Analog Devices has developed new 6- and 12-channel clock buffers for high-speed applications requiring low jitter. The 12-channel ADCLK954 LVPECL and ADCLK854 LVDS/CMOS and 6-channel ADCLK946 LVPECL and ADCLK846 LVDS provide jitter as low as 75 fs for the LVPECL (low voltage positive emitter coupled logic) fanout buffers and 100 fs for the LVDS (low voltage differential signalling)/CMOS variants. In addition, the ADCLK9xx clock buffers offer an extremely low 9 ps skew. The ADCLK854 also offers 24 CMOS (complementary metal oxide semiconductor) channels.

With these specifications, the clock buffers are effective for clocking high-speed ADCs (analog-to-digital converters) and DACs (digital-to-analog converters) and are suitable for high-performance applications, such as wireless infrastructure equipment, medical imaging and industrial applications that require high-speed, high-channel density and high-timing performance.

All the devices allow design engineers to benefit from the full resolution and performance of high-speed ADCs and DACs while maintaining low power of 12 mW per channel at 100 MHz operation. The ADCLK854 offers two selectable inputs and a sleep mode feature. The IN_SEL pin-state determines which input fans out to the outputs. The SLEEP pin enables a sleep mode to power down the device. The inputs accept various single-ended and differential logic levels, including LVPECL, LVDS, HSTL (high-speed transceiver logic), CML (current-mode logic) and CMOS. The 4,8 GHz ADCLK954 has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with 100 ohm on-chip termination resistors and may operate with either differential or single-ended clock sources.

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